extdma.c

这是三星公司的arm7 s3c44b0x芯片的所有外设中断程序

//44BTEST : extdma.c
#include <string.h>
#include "..\inc\44b.h"
#include "..\inc\44blib.h"
#include "..\inc\def.h"
void _Zdma0XdreqHandshakeUnit8bit(void);
void _Zdma0XdreqHandshakeUnit16bit(void);
void _Zdma0XdreqHandshakeUnit32bit(void);
void _Zdma0XdreqHandshakeBlock16bit(void);
void _Zdma0XdreqWholeUnit16bit(void);
void _Zdma0XdreqWholeBlock16bit(void);
void _Zdma0XdreqHandshakeOntheflyRd16bit(void);
void _Zdma0XdreqHandshakeOntheflyWr16bit(void);
#define BUS8 (0)
#define BUS16 (1)
#define BUS32 (2)
#define ENWAIT (1)
#define SRAMBE03 (1)
//PG3 = DMAMODE0
//PG4 = DMAMODE1
//PE4 = nDMASTART
//PE5 = D16_32ENABLE
#define SET_XDREQ16() rPDATG=(rPDATG&~(3<<3))|(0x1<<3)
#define SET_XDREQ1() rPDATG=(rPDATG&~(3<<3))|(0x2<<3)
#define START_XDREQ() {rPDATE=(rPDATE&~(1<<4))|(0x0<<4);\
rPDATE=(rPDATE&~(1<<4))|(0x1<<4);}
//DMAMODE[1:0]: 01b= one time request
// 10b= 16 time requests
#define B2_Tacs (0x0) //0clk
#define B2_Tcos (0x0) //0clk
//#define B2_Tacc (0x2) //3clk
#define B2_Tacc (0x6) //10clk
#define B2_Tcoh (0x0) //0clk
#define B2_Tah (0x0) //0clk
#define B2_Tacp (0x0) //2clk
#define B2_PMC (0x0) //no page mode
volatile int isZdma0Done;
//Verilog code for data bus pins of the EPM7256A
//assign data[3:0] = (!nGCS && !nOE ) ? wdata:4'bz;
//assign data[23:4]= (!nGCS && !nOE && !nUDE) ? addr[19:0]:20'bz;
void __irq IsrZdma0Done(void)
{
	rI_ISPC=BIT_ZDMA0;
	isZdma0Done=1;
}
void Test_ZDma0Xdreq(void)
{
	U32 savePCONC;
	rINTMSK=BIT_GLOBAL;
	pISR_ZDMA0=(U32)IsrZdma0Done;
	rINTMSK=~(BIT_GLOBAL|BIT_ZDMA0);
	Cache_Flush(); //to clear the cache memory.
	savePCONC=rPCONC;
	rPCONC=0xaaaaaaaa; //DATA[16:31] is selected.
	rPCONF=rPCONF&(~(0xf<<6))|(0xf<<6);//PF3=nXDACK0,PF4=nXDREQ0
	rPCONE=rPCONE&(~(3))|(3); //PE0=CLKOUT
	rPDATG=rPDATG&(3<<3);
	rPCONG=rPCONG&~(0xf<<6)|(5<<6); //PG3,4=OUTPUT
	rPDATE=rPDATE&~(1<<4)|(1<<4); //PE4=H,PE5=H
	rPCONE=rPCONE&~(0xf<<8)|(5<<8); //PE4,PE5=OUTPUT
	rPDATE=rPDATE&~(1<<5)|(0<<5);//nUDE=L(PE5=L) to enable EPM7256A d[23:4]
	Uart_Printf("Test Menu for ZDMA0 nXDREQ/nXDACK\n");
	Uart_Printf("1: Handshake/unit/8bit src:GCS2(8) dst:SDRAM(16)\n");
	Uart_Printf("2: Handshake/unit/16bit src:GCS2(16) dst:SDRAM(16)\n");
	Uart_Printf("3: Handshake/unit/32bit src:GCS2(32) dst:SDRAM(16)\n");
	Uart_Printf("4: Handshake/block/16bit src:GCS2(16) dst:SDRAM(16)\n");
	Uart_Printf("5: Whole/unit/16bit src:GCS0(8) dst:SDRAM(16)\n");
	Uart_Printf("6: Whole/block/16bit src:GCS0(8) dst:SDRAM(16)\n");
	Uart_Printf("7: Handshake/of_rd/16bit src:GCS2(16)\n");
	Uart_Printf("8: Handshake/of_wr/16bit dst:GCS2(16)\n");
	Uart_Printf("Select the item?\n");
	switch(Uart_Getch())
	{
	case '1':
		_Zdma0XdreqHandshakeUnit8bit();
		break;
	case '2':
		_Zdma0XdreqHandshakeUnit16bit();
		break;
	case '3':
		_Zdma0XdreqHandshakeUnit32bit();
		break;
	case '4':
		_Zdma0XdreqHandshakeBlock16bit();
		break;
	case '5':
		_Zdma0XdreqWholeUnit16bit();
		break;
	case '6':
		_Zdma0XdreqWholeBlock16bit();
		break;
	case '7':
		_Zdma0XdreqHandshakeOntheflyRd16bit();
		break;
	case '8':
		_Zdma0XdreqHandshakeOntheflyWr16bit();
		break;
	default:
		break;
	}
	rPCONC=savePCONC;
}
void _Zdma0XdreqHandshakeUnit8bit(void)
{
	int i;
	static U8 bufDst[16];
	rBWSCON=rBWSCON&(~0xf00)|(BUS8<<8);
	rBANKCON2=((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC));
	Uart_Printf("[ZDMA0,HandShake,unit,8bit Test,B2->SDRAM]\n");
	Uart_Printf("NOTE:Ignore bit[3:0]!!\n");
	for(i=0;i<16;i++)
		bufDst[i]=0;
	isZdma0Done=0;
	rNCACHBE0=( ( (((unsigned)bufDst+16*1)>>12) +1 )<<16 )|((unsigned)bufDst>>12);
	rINTMSK=~(BIT_GLOBAL|BIT_ZDMA0);
	rZDISRC0=(U32)0x4001230|(0<<30)|(1<<28); // byte,inc
	rZDIDES0=(U32)bufDst|((U32)2<<30)|(1<<28); // normal,inc
	rZDICNT0=16|(0x0<<30)|(0x0<<28)|(0x1<<26)|(0x2<<24)|(0x3<<22)|(0x1<<21)|(0<<20);
	//nXDREQ0,handshake,unit,terminal_int,auto-reload,disable DMA,
	rZDICNT0 |= (0x1<<20);//enable
	rZDCON0=0x0; // nXDREQ0 enable,CMD=no_command.
	SET_XDREQ16();
	START_XDREQ();
	while(isZdma0Done==0);
	for(i=0;i<16;i++)
		Uart_Printf( "%2x,",*((U8 *)0x4001230+i) );
	Uart_Printf("\n");
	for(i=0;i<16;i++)
		Uart_Printf("%2x,",bufDst[i]);
	Uart_Printf("\n");
	Cache_Flush();
	rNCACHBE0=0;
}
void _Zdma0XdreqHandshakeUnit16bit(void)
{
	int i;
	static U16 bufDst[16];
	static U16 bufSrc[16];
	rBWSCON=rBWSCON&(~0xf00)|(BUS16<<8);
	rBANKCON2=((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC));
	Uart_Printf("[ZDMA0,HandShake,unit,16bit Test,SDRAM->SDRAM]\n");
	for(i=0;i<16;i++)
	{
		bufSrc[i]=i;
		bufDst[i]=0;
	}
	isZdma0Done=0;
	rNCACHBE0=( ( (((unsigned)bufDst+16*4)>>12) +1 )<<16 )|((unsigned)bufDst>>12);
	rINTMSK=~(BIT_GLOBAL|BIT_ZDMA0);
	rZDISRC0=(U32)bufSrc|(1<<30)|(1<<28); // half-word,inc
	rZDIDES0=(U32)bufDst|((U32)2<<30)|(1<<28); // normal,inc
	rZDICNT0=32|(0x0<<30)|(0x0<<28)|(0x1<<26)|(0x2<<24)|(0x3<<22)|(0x1<<21)|(0<<20);
	//nXDREQ0,handshake,unit,terminal_int,auto-reload,disable DMA,
	rZDICNT0 |= (0x1<<20);//enable
	rZDCON0=0x0; // nXDREQ0 enable,CMD=no_command.
	SET_XDREQ16();
	START_XDREQ();
	while(isZdma0Done==0);
	for(i=0;i<16;i++)
		Uart_Printf("%x,",*((U16 *)bufSrc+i));
	Uart_Printf("\n");
	for(i=0;i<16;i++)
		Uart_Printf("%x,",*((U16 *)bufDst+i));
	Uart_Printf("\n");
	Cache_Flush();
	rNCACHBE0=0;
}

void _Zdma0XdreqHandshakeUnit32bit(void)
{
	int i;
	static U32 bufDst[16];
	rBWSCON=rBWSCON&(~0xf00)|(BUS32<<8);
	rBANKCON2=((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC));
	Uart_Printf("[ZDMA0,HandShake,unit,32bit Test,B2->SDRAM]\n");
	Uart_Printf("NOTE:Ignore bit[3:0],bit[31:24]!!\n");
	for(i=0;i<16;i++)
		bufDst[i]=0;
	isZdma0Done=0;
	rNCACHBE0=( ( (((unsigned)bufDst+16*4)>>12) +1 )<<16 )|((unsigned)bufDst>>12);
	rINTMSK=~(BIT_GLOBAL|BIT_ZDMA0);
	rZDISRC0=(U32)0x4001230|((U32)2<<30)|(1<<28); // word,inc
	rZDIDES0=(U32)bufDst|((U32)2<<30)|(1<<28); // normal,inc
	rZDICNT0=64|(0x0<<30)|(0x0<<28)|(0x1<<26)|(0x2<<24)|(0x3<<22)|(0x1<<21)|(0<<20);
	//nXDREQ0,handshake,unit,terminal_int,auto-reload,disable DMA,
	rZDICNT0 |= (0x1<<20);//enable
	rZDCON0=0x0; // nXDREQ0 enable,CMD=no_command.
	SET_XDREQ16();
	START_XDREQ();
	while(isZdma0Done==0);
	for(i=0;i<16;i++)
	{
		Uart_Printf("%8x,",*((U32 *)0x4001230+i));
		if(i%8==7)Uart_Printf("\n");
	}
	for(i=0;i<16;i++)
	{
		Uart_Printf("%8x,",bufDst[i]);
		if(i%8==7)Uart_Printf("\n");
	}
	Cache_Flush();
	rNCACHBE0=0;
}
void _Zdma0XdreqHandshakeBlock16bit(void)
{
	int i;
	static U16 bufDst[128];
	rBWSCON=rBWSCON&(~0xf00)|(BUS16<<8);
	rBANKCON2=((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC));
	Uart_Printf("[ZDMA0,HandShake,block,16bit Test,B2->SDRAM]\n");
	Uart_Printf("NOTE:Ignore bit[3:0]\n");
	for(i=0;i<128;i++)
		bufDst[i]=0;
	isZdma0Done=0;
	rNCACHBE0=( ( (((unsigned)bufDst+128*2)>>12) +1 )<<16 )|((unsigned)bufDst>>12);
	rINTMSK=~(BIT_GLOBAL|BIT_ZDMA0);
	rZDISRC0=(U32)0x4001200|((U32)2<<30)|(1<<28); // word,inc
	rZDIDES0=(U32)bufDst|((U32)2<<30)|(1<<28); // normal,inc
	rZDICNT0=256|(0x0<<30)|(0x0<<28)|(0x2<<26)|(0x2<<24)|(0x3<<22)|(0x1<<21)|(0<<20);
	//nXDREQ0,handshake,block,terminal_int,auto-reload,disable DMA,
	rZDICNT0 |= (0x1<<20);//enable
	rZDCON0=0x0; // nXDREQ0 enable,CMD=no_command.
	SET_XDREQ16();
	START_XDREQ();
	while(isZdma0Done==0)
	{
		Uart_Printf("rZDCCNT0=%x\r",rZDCCNT0);
	}
	Uart_Printf("Correct data:200x,202x,204x,....,2fex\n");
	/*
	for(i=0;i<128;i++)
	{
	Uart_Printf("%4x,",*((U16 *)0x4001200+i));
	if(i%16==15)Uart_Printf("\n");
	}
	*/
	for(i=0;i<128;i++)
	{
		Uart_Printf("%4x,",bufDst[i]);
		if(i%8==7)Uart_Printf("\n");
	}
	Cache_Flush();
	rNCACHBE0=0;
}

void _Zdma0XdreqWholeUnit16bit(void)
{
	int i;
	static U16 bufDst[16];
	rBWSCON=rBWSCON&(~0xf00)|(BUS16<<8);
	rBANKCON2=((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC));
	Uart_Printf("[ZDMA0,Whole,unit,16bit Test,B2->SDRAM]\n");
	Uart_Printf("NOTE:Ignore bit[3:0]\n");
	for(i=0;i<16;i++)
		bufDst[i]=0;
	isZdma0Done=0;
	rNCACHBE0=( ( (((unsigned)bufDst+16*2)>>12) +1 )<<16 )|((unsigned)bufDst>>12);
	rINTMSK=~(BIT_GLOBAL|BIT_ZDMA0);
	rZDISRC0=(U32)0x4001200|((U32)1<<30)|(1<<28); // half-word,inc
	rZDIDES0=(U32)bufDst|((U32)2<<30)|(1<<28); // normal,inc
	rZDICNT0=32|(0x0<<30)|(0x2<<28)|(0x1<<26)|(0x2<<24)|(0x3<<22)|(0x1<<21)|(0<<20);
	//nXDREQ0,whole,unit,terminal_int,auto-reload,disable DMA,
	rZDICNT0 |= (0x1<<20);//enable
	rZDCON0=0x0; // nXDREQ0 enable,CMD=no_command.
	SET_XDREQ1();
	START_XDREQ();
	while(isZdma0Done==0);
	Uart_Printf("Correct data:200x,202x,204x,....,21ex\n");
	for(i=0;i<16;i++)
		Uart_Printf("%x,",*((U16 *)bufDst+i));
	Uart_Printf("\n");
	Cache_Flush();
	rNCACHBE0=0;
}
void _Zdma0XdreqWholeBlock16bit(void)
{
	int i;
	static U16 bufDst[128];
	rBWSCON=rBWSCON&(~0xf00)|(BUS16<<8);
	rBANKCON2=((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC));
	Uart_Printf("[ZDMA0,whole,block,16bit Test,B2->SDRAM]\n");
	Uart_Printf("NOTE:Ignore bit[3:0]\n");
	for(i=0;i<128;i++)
		bufDst[i]=0;
	isZdma0Done=0;
	rNCACHBE0=( ( (((unsigned)bufDst+128*2)>>12) +1 )<<16 )|((unsigned)bufDst>>12);
	rINTMSK=~(BIT_GLOBAL|BIT_ZDMA0);
	rZDISRC0=(U32)0x4001200|((U32)2<<30)|(1<<28); // word,inc
	rZDIDES0=(U32)bufDst|((U32)2<<30)|(1<<28); // normal,inc
	rZDICNT0=256|(0x0<<30)|(0x2<<28)|(0x2<<26)|(0x2<<24)|(0x3<<22)|(0x1<<21)|(0<<20);
	//nXDREQ0,whole,block,terminal_int,auto-reload,disable DMA,
	rZDICNT0 |= (0x1<<20);//enable
	rZDCON0=0x0; // nXDREQ0 enable,CMD=no_command.
	SET_XDREQ1();
	START_XDREQ();
	while(isZdma0Done==0)
	{
		Uart_Printf("rZDCCNT0=%x\r",rZDCCNT0);
	}
	Uart_Printf("Correct data:200x,202x,204x,....,2fex\n");
	for(i=0;i<128;i++)
	{
		Uart_Printf("%4x,",bufDst[i]);
		if(i%8==7)
			Uart_Printf("\n");
	}
	Cache_Flush();
	rNCACHBE0=0;
}
void _Zdma0XdreqHandshakeOntheflyRd16bit(void)
{
	rBWSCON=rBWSCON&(~0xf00)|(BUS16<<16);
	rBANKCON2=((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC));
	Uart_Printf("[ZDMA0,HandShake,read_OTF,16bit Test,B2(src)]\n");
	Uart_Printf("NOTE:Ignore bit[3:0]\n");
	Uart_Printf("Check the data using a logic analyzer.\n");
	isZdma0Done=0;
	rNCACHBE0=( (((unsigned)0x6000000)>>12)<<16 )|((unsigned)0x4000000>>12);
	rINTMSK=~(BIT_GLOBAL|BIT_ZDMA0);
	rZDISRC0=(U32)0x4001230|((U32)2<<30)|(1<<28); // word,inc
	rZDIDES0=0|((U32)2<<30)|(1<<28); // normal,inc
	rZDICNT0=32|(0x0<<30)|(0x0<<28)|(0x3<<26)|(0x2<<24)|(0x3<<22)|(0x1<<21)|(0<<20);
	//nXDREQ0,handshake,read_OTF,terminal_int,auto-reload,disable DMA,
	rZDICNT0 |= (0x1<<20);//enable
	rZDCON0=0x0; // nXDREQ0 enable,CMD=no_command.
	SET_XDREQ16();
	START_XDREQ();
	while(isZdma0Done==0)
	{
		Uart_Printf("rZDCCNT0=%x\r",rZDCCNT0);
	}
	Cache_Flush();
	rNCACHBE0=0;
}
void _Zdma0XdreqHandshakeOntheflyWr16bit(void)
{
	rBWSCON=rBWSCON&(~0xf00)|(BUS16<<16);
	rBANKCON2=((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC));
	Uart_Printf("[ZDMA0,HandShake,write_OTF,16bit Test,B2(dst)]\n");
	Uart_Printf("Check your data using a logic analyzer.\n");
	isZdma0Done=0;
	rNCACHBE0=( (((unsigned)0x6000000)>>12)<<16 )|((unsigned)0x4000000>>12);
	rINTMSK=~(BIT_GLOBAL|BIT_ZDMA0);
	rZDISRC0=0x0|((U32)2<<30)|(1<<28); // word,inc
	rZDIDES0=(U32)0x4001230|((U32)2<<30)|(1<<28); // normal,inc
	rZDICNT0=32|(0x0<<30)|(0x0<<28)|(0x3<<26)|(0x3<<24)|(0x3<<22)|(0x0<<21)|(0<<20);
	//nXDREQ0,handshake,write_OTF,terminal_int,auto-reload,disable DMA,
	rZDICNT0 |= (0x1<<20);//enable
	rZDCON0=0x0; // nXDREQ0 enable,CMD=no_command.
	SET_XDREQ16();
	START_XDREQ();
	while(isZdma0Done==0)
	{
		Uart_Printf("rZDCCNT0=%x\r",rZDCCNT0);
	}
	Cache_Flush();
	rNCACHBE0=0;
}