ppc860siu.h

这是motorola公司的powerpc芯片上的嵌入式linux上的驱动程序和测试程序

#define MCR_MCLF_12X	0x00000c00	/* The Cmd Loop is executed 12 times */
#define MCR_MCLF_13X	0x00000d00	/* The Cmd Loop is executed 13 times */
#define MCR_MCLF_14X	0x00000e00	/* The Cmd Loop is executed 14 times */
#define MCR_MCLF_15X	0x00000f00	/* The Cmd Loop is executed 15 times */
#define MCR_MCLF_16X	0x00000000	/* The Cmd Loop is executed 16 times */
#define MCR_MAD_MSK	0x0000003f	/* Machine Address mask */

/* Machine A Mode Register bit definition (MAMR - 0x170) */

#define MAMR_PTA_MSK	0xff000000	/* Periodic Timer A period mask */
#define MAMR_PTA_SHIFT	0x00000018	/* Periodic Timer A period shift */
#define MAMR_PTAE	0x00800000	/* Periodic Timer A Enable */
#define MAMR_AMA_MSK	0x00700000	/* Addess Multiplexing size A */
#define MAMR_AMA_TYPE_0	0x00000000	/* Addess Multiplexing Type 0 */
#define MAMR_AMA_TYPE_1	0x00100000	/* Addess Multiplexing Type 1 */
#define MAMR_AMA_TYPE_2	0x00200000	/* Addess Multiplexing Type 2 */
#define MAMR_AMA_TYPE_3	0x00300000	/* Addess Multiplexing Type 3 */
#define MAMR_AMA_TYPE_4	0x00400000	/* Addess Multiplexing Type 4 */
#define MAMR_AMA_TYPE_5	0x00500000	/* Addess Multiplexing Type 5 */
#define MAMR_DSA_MSK	0x00060000	/* Disable Timer period mask */
#define MAMR_DSA_1_CYCL	0x00000000	/* 1 cycle Disable Period */
#define MAMR_DSA_2_CYCL	0x00020000	/* 2 cycle Disable Period */
#define MAMR_DSA_3_CYCL	0x00040000	/* 3 cycle Disable Period */
#define MAMR_DSA_4_CYCL	0x00060000	/* 4 cycle Disable Period */
#define MAMR_G0CLA_MSK	0x0000e000	/* General Line 0 Control A */
#define MAMR_G0CLA_A12	0x00000000	/* General Line 0 : A12 */
#define MAMR_G0CLA_A11	0x00002000	/* General Line 0 : A11 */
#define MAMR_G0CLA_A10	0x00004000	/* General Line 0 : A10 */
#define MAMR_G0CLA_A9	0x00006000	/* General Line 0 : A9 */
#define MAMR_G0CLA_A8	0x00008000	/* General Line 0 : A8 */
#define MAMR_G0CLA_A7	0x0000a000	/* General Line 0 : A7 */
#define MAMR_G0CLA_A6	0x0000b000	/* General Line 0 : A6 */
#define MAMR_G0CLA_A5	0x0000e000	/* General Line 0 : A5 */
#define MAMR_GPL_A4DIS	0x00001000	/* GPL_A4 ouput line Disable */
#define MAMR_RLFA_MSK	0x00000f00	/* Read Loop Field A mask */
#define MAMR_RLFA_1X	0x00000100	/* The Read Loop is executed 1 time */
#define MAMR_RLFA_2X	0x00000200	/* The Read Loop is executed 2 times */
#define MAMR_RLFA_3X	0x00000300	/* The Read Loop is executed 3 times */
#define MAMR_RLFA_4X	0x00000400	/* The Read Loop is executed 4 times */
#define MAMR_RLFA_5X	0x00000500	/* The Read Loop is executed 5 times */
#define MAMR_RLFA_6X	0x00000600	/* The Read Loop is executed 6 times */
#define MAMR_RLFA_7X	0x00000700	/* The Read Loop is executed 7 times */
#define MAMR_RLFA_8X	0x00000800	/* The Read Loop is executed 8 times */
#define MAMR_RLFA_9X	0x00000900	/* The Read Loop is executed 9 times */
#define MAMR_RLFA_10X	0x00000a00	/* The Read Loop is executed 10 times */
#define MAMR_RLFA_11X	0x00000b00	/* The Read Loop is executed 11 times */
#define MAMR_RLFA_12X	0x00000c00	/* The Read Loop is executed 12 times */
#define MAMR_RLFA_13X	0x00000d00	/* The Read Loop is executed 13 times */
#define MAMR_RLFA_14X	0x00000e00	/* The Read Loop is executed 14 times */
#define MAMR_RLFA_15X	0x00000f00	/* The Read Loop is executed 15 times */
#define MAMR_RLFA_16X	0x00000000	/* The Read Loop is executed 16 times */
#define MAMR_WLFA_MSK	0x000000f0	/* Write Loop Field A mask */
#define MAMR_WLFA_1X	0x00000010	/* The Write Loop is executed 1 time */
#define MAMR_WLFA_2X	0x00000020	/* The Write Loop is executed 2 times */
#define MAMR_WLFA_3X	0x00000030	/* The Write Loop is executed 3 times */
#define MAMR_WLFA_4X	0x00000040	/* The Write Loop is executed 4 times */
#define MAMR_WLFA_5X	0x00000050	/* The Write Loop is executed 5 times */
#define MAMR_WLFA_6X	0x00000060	/* The Write Loop is executed 6 times */
#define MAMR_WLFA_7X	0x00000070	/* The Write Loop is executed 7 times */
#define MAMR_WLFA_8X	0x00000080	/* The Write Loop is executed 8 times */
#define MAMR_WLFA_9X	0x00000090	/* The Write Loop is executed 9 times */
#define MAMR_WLFA_10X	0x000000a0	/* The Write Loop is executed 10 times*/
#define MAMR_WLFA_11X	0x000000b0	/* The Write Loop is executed 11 times*/
#define MAMR_WLFA_12X	0x000000c0	/* The Write Loop is executed 12 times*/
#define MAMR_WLFA_13X	0x000000d0	/* The Write Loop is executed 13 times*/
#define MAMR_WLFA_14X	0x000000e0	/* The Write Loop is executed 14 times*/
#define MAMR_WLFA_15X	0x000000f0	/* The Write Loop is executed 15 times*/
#define MAMR_WLFA_16X	0x00000000	/* The Write Loop is executed 16 times*/
#define MAMR_TLFA_MSK	0x0000000f	/* Timer Loop Field A mask */
#define MAMR_TLFA_1X	0x00000001	/* The Timer Loop is executed 1 time */
#define MAMR_TLFA_2X	0x00000002	/* The Timer Loop is executed 2 times */
#define MAMR_TLFA_3X	0x00000003	/* The Timer Loop is executed 3 times */
#define MAMR_TLFA_4X	0x00000004	/* The Timer Loop is executed 4 times */
#define MAMR_TLFA_5X	0x00000005	/* The Timer Loop is executed 5 times */
#define MAMR_TLFA_6X	0x00000006	/* The Timer Loop is executed 6 times */
#define MAMR_TLFA_7X	0x00000007	/* The Timer Loop is executed 7 times */
#define MAMR_TLFA_8X	0x00000008	/* The Timer Loop is executed 8 times */
#define MAMR_TLFA_9X	0x00000009	/* The Timer Loop is executed 9 times */
#define MAMR_TLFA_10X	0x0000000a	/* The Timer Loop is executed 10 times*/
#define MAMR_TLFA_11X	0x0000000b	/* The Timer Loop is executed 11 times*/
#define MAMR_TLFA_12X	0x0000000c	/* The Timer Loop is executed 12 times*/
#define MAMR_TLFA_13X	0x0000000d	/* The Timer Loop is executed 13 times*/
#define MAMR_TLFA_14X	0x0000000e	/* The Timer Loop is executed 14 times*/
#define MAMR_TLFA_15X	0x0000000f	/* The Timer Loop is executed 15 times*/
#define MAMR_TLFA_16X	0x00000000	/* The Timer Loop is executed 16 times*/

/* Machine B Mode Register bit definition (MBMR - 0x174) */

#define MAMR_PTB_MSK	0xff000000	/* Periodic Timer B period mask */
#define MAMR_PTBE	0x00800000	/* Periodic Timer B Enable */
#define MAMR_AMB_MSK	0x00700000	/* Addess Multiplex size B */
#define MAMR_DSB_MSK	0x00060000	/* Disable Timer period mask */
#define MAMR_DSB_1_CYCL	0x00000000	/* 1 cycle Disable Period */
#define MAMR_DSB_2_CYCL	0x00020000	/* 2 cycle Disable Period */
#define MAMR_DSB_3_CYCL	0x00040000	/* 3 cycle Disable Period */
#define MAMR_DSB_4_CYCL	0x00060000	/* 4 cycle Disable Period */
#define MAMR_G0CLB_MSK	0x0000e000	/* General Line 0 Control B */
#define MAMR_G0CLB_A12	0x00000000	/* General Line 0 : A12 */
#define MAMR_G0CLB_A11	0x00002000	/* General Line 0 : A11 */
#define MAMR_G0CLB_A10	0x00004000	/* General Line 0 : A10 */
#define MAMR_G0CLB_A9	0x00006000	/* General Line 0 : A9 */
#define MAMR_G0CLB_A8	0x00008000	/* General Line 0 : A8 */
#define MAMR_G0CLB_A7	0x0000a000	/* General Line 0 : A7 */
#define MAMR_G0CLB_A6	0x0000b000	/* General Line 0 : A6 */
#define MAMR_G0CLB_A5	0x0000e000	/* General Line 0 : A5 */
#define MAMR_GPL_B4DIS	0x00001000	/* GPL_B4 ouput line Disable */
#define MAMR_RLFB_MSK	0x00000f00	/* Read Loop Field B mask */
#define MAMR_RLFB_1X	0x00000100	/* The Read Loop is executed 1 time */
#define MAMR_RLFB_2X	0x00000200	/* The Read Loop is executed 2 times */
#define MAMR_RLFB_3X	0x00000300	/* The Read Loop is executed 3 times */
#define MAMR_RLFB_4X	0x00000400	/* The Read Loop is executed 4 times */
#define MAMR_RLFB_5X	0x00000500	/* The Read Loop is executed 5 times */
#define MAMR_RLFB_6X	0x00000600	/* The Read Loop is executed 6 times */
#define MAMR_RLFB_7X	0x00000700	/* The Read Loop is executed 7 times */
#define MAMR_RLFB_8X	0x00000800	/* The Read Loop is executed 8 times */
#define MAMR_RLFB_9X	0x00000900	/* The Read Loop is executed 9 times */
#define MAMR_RLFB_10X	0x00000a00	/* The Read Loop is executed 10 times */
#define MAMR_RLFB_11X	0x00000b00	/* The Read Loop is executed 11 times */
#define MAMR_RLFB_12X	0x00000c00	/* The Read Loop is executed 12 times */
#define MAMR_RLFB_13X	0x00000d00	/* The Read Loop is executed 13 times */
#define MAMR_RLFB_14X	0x00000e00	/* The Read Loop is executed 14 times */
#define MAMR_RLFB_15X	0x00000f00	/* The Read Loop is executed 15 times */
#define MAMR_RLFB_16X	0x00000000	/* The Read Loop is executed 16 times */
#define MAMR_WLFB_MSK	0x000000f0	/* Write Loop Field B mask */
#define MAMR_WLFB_1X	0x00000010	/* The Write Loop is executed 1 time */
#define MAMR_WLFB_2X	0x00000020	/* The Write Loop is executed 2 times */
#define MAMR_WLFB_3X	0x00000030	/* The Write Loop is executed 3 times */
#define MAMR_WLFB_4X	0x00000040	/* The Write Loop is executed 4 times */
#define MAMR_WLFB_5X	0x00000050	/* The Write Loop is executed 5 times */
#define MAMR_WLFB_6X	0x00000060	/* The Write Loop is executed 6 times */
#define MAMR_WLFB_7X	0x00000070	/* The Write Loop is executed 7 times */
#define MAMR_WLFB_8X	0x00000080	/* The Write Loop is executed 8 times */
#define MAMR_WLFB_9X	0x00000090	/* The Write Loop is executed 9 times */
#define MAMR_WLFB_10X	0x000000a0	/* The Write Loop is executed 10 times*/
#define MAMR_WLFB_11X	0x000000b0	/* The Write Loop is executed 11 times*/
#define MAMR_WLFB_12X	0x000000c0	/* The Write Loop is executed 12 times*/
#define MAMR_WLFB_13X	0x000000d0	/* The Write Loop is executed 13 times*/
#define MAMR_WLFB_14X	0x000000e0	/* The Write Loop is executed 14 times*/
#define MAMR_WLFB_15X	0x000000f0	/* The Write Loop is executed 15 times*/
#define MAMR_WLFB_16X	0x00000000	/* The Write Loop is executed 16 times*/
#define MAMR_TLFB_MSK	0x0000000f	/* Timer Loop Field B mask */
#define MAMR_TLFB_1X	0x00000001	/* The Timer Loop is executed 1 time */
#define MAMR_TLFB_2X	0x00000002	/* The Timer Loop is executed 2 times */
#define MAMR_TLFB_3X	0x00000003	/* The Timer Loop is executed 3 times */
#define MAMR_TLFB_4X	0x00000004	/* The Timer Loop is executed 4 times */
#define MAMR_TLFB_5X	0x00000005	/* The Timer Loop is executed 5 times */
#define MAMR_TLFB_6X	0x00000006	/* The Timer Loop is executed 6 times */
#define MAMR_TLFB_7X	0x00000007	/* The Timer Loop is executed 7 times */
#define MAMR_TLFB_8X	0x00000008	/* The Timer Loop is executed 8 times */
#define MAMR_TLFB_9X	0x00000009	/* The Timer Loop is executed 9 times */
#define MAMR_TLFB_10X	0x0000000a	/* The Timer Loop is executed 10 times*/
#define MAMR_TLFB_11X	0x0000000b	/* The Timer Loop is executed 11 times*/
#define MAMR_TLFB_12X	0x0000000c	/* The Timer Loop is executed 12 times*/
#define MAMR_TLFB_13X	0x0000000d	/* The Timer Loop is executed 13 times*/
#define MAMR_TLFB_14X	0x0000000e	/* The Timer Loop is executed 14 times*/
#define MAMR_TLFB_15X	0x0000000f	/* The Timer Loop is executed 15 times*/
#define MAMR_TLFB_16X	0x00000000	/* The Timer Loop is executed 16 times*/

/* Time Base Status and Contol register bit definition (TBSCR - 0x200) */

#if	FALSE				/* XXX TPR TO verify */

#define TBSCR_TBIRQ0	0x0100	/* Time Base Interrupt Request 0 */
#define TBSCR_TBIRQ1	0x0200	/* Time Base Interrupt Request 1 */
#define TBSCR_TBIRQ2	0x0400	/* Time Base Interrupt Request 2 */
#define TBSCR_TBIRQ3	0x0800	/* Time Base Interrupt Request 3 */
#define TBSCR_TBIRQ4	0x1000	/* Time Base Interrupt Request 4 */
#define TBSCR_TBIRQ5	0x2000	/* Time Base Interrupt Request 5 */
#define TBSCR_TBIRQ6	0x4000	/* Time Base Interrupt Request 6 */
#define TBSCR_TBIRQ7	0x8000	/* Time Base Interrupt Request 7 */

#endif

#define TBSCR_REFA	0x0080	/* Reference Interrupt Status A */
#define TBSCR_REFB	0x0040	/* Reference Interrupt Status B */
#define TBSCR_REFAE	0x0008	/* Second Interrupt Enable A */
#define TBSCR_REFBE	0x0004	/* Second Interrupt Enable B */
#define TBSCR_TBF	0x0002	/* Time Base Freeze */
#define TBSCR_TBE	0x0001	/* Time Base Enable */

/* Real Time Clock Status and Control register bit definition (RTCSC - 0x220) */

#define RTCSC_RTCIRQ
#define RTCSC_SEC	0x0080		/* Once per Second interrupt */
#define RTCSC_ALR	0x0040		/* Alarm interrupt */
#define RTCSC_38K	0x0010		/* Real Time Clock at 38.4 KHz */
#define RTCSC_SIE	0x0008		/* Second Interrupt Enable */
#define RTCSC_ALE	0x0004		/* Alarm Interrupt Enable */
#define RTCSC_RTF	0x0002		/* Real Time Clock Freeze */
#define RTCSC_RTE	0x0001		/* Real Time Clock Enable */

/* PIT Status and Control Register bit definition (PISCR - 0x0240) */

#define PISCR_PIRQ
#define PISCR_PS	0x0080		/* Periodic interrupt Status */
#define PISCR_PIE	0x0004		/* Periodic Interrupt Enable */
#define PISCR_PITF	0x0002		/* Periodic Interrupt Timer Freeze */
#define PISCR_PTE	0x0001		/* Periodic Timer Enable */

/* System Clock Control Register bit definition (SCCR - 0x280) */

#define SCCR_COM_MSK	0x60000000	/* Clock Output Mode Mask */
#define SCCR_TBS	0x02000000	/* Time Base Source */
#define SCCR_RTDIV	0x01000000	/* RTC Clock Dive */
#define SCCR_RTSEL	0x00800000	/* RTC circuit input source select */
#define SCCR_CRQEN	0x00400000	/* CPM Request Enable */
#define SCCR_PRQEN	0x00200000	/* Power Management Request Enable */
#define SCCR_DFSYNC_MSK	0x00006000	/* Division Factor of SyncCLK Mask */
#define SCCR_DFBRG_MSK	0x00001800	/* Division Factor of BRGCLK Mask */
#define SCCR_DFBRG_SHIFT    0x000c	/* Division Factor of BRGCLK shift */
#define SCCR_DFNL_MSK	0x00000700	/* Division Factor Low Frequency Mask */
#define SCCR_DFNH_MSK	0x000000e0	/* Division Factor High Frequency Mask*/
#define SCCR_DFLCD_MSK	0x0000001c	/* Division Factor of LCD Clock Mask */
#define SCCR_DFALCD_MSK	0x00000002	/* Add. Division Factor of LCD Clock */

/* Pll, Low Power and Reset Control Register bit definition (PLPRCR - 284) */

#define PLPRCR_MF_MSK	0xfff00000	/* Multiplication factor bits */
#define PLPRCR_MF_SHIFT	0x00000014	/* Multiplication factor shift value */
#define PLPRCR_SPLSS	0x00008000	/* SPLL Lock Status Sticky bit */
#define PLPRCR_TEXPS	0x00004000	/* TEXP Status */
#define PLPRCR_TMIST	0x00001000	/* Timers Interrupt Status */
#define PLPRCR_CSRC	0x00000400	/* Clock Source */
#define PLPRCR_LPM_MSK	0x00000300	/* Low Power Mode mask */
#define	PLPRCR_LPM_NORMAL 0x00000000	/* normal power management mode */
#define	PLPRCR_LPM_DOZE	  0x00000100	/* doze power management mode */
#define	PLPRCR_LPM_SLEEP  0x00000200	/* sleep power management mode */
#define	PLPRCR_LPM_DEEP_SLEEP 0x00000300 /* deep sleep power mgt mode */
#define	PLPRCR_LPM_DOWN   0x00000300	/* down power management mode */
#define PLPRCR_CSR	0x00000080	/* CheskStop Reset value */
#define PLPRCR_LOLRE	0x00000040	/* Loss Of Lock Reset Enable */
#define PLPRCR_FIOPD	0x00000020	/* Force I/O Pull Down */

/* LCD register bit definitions */

#define LCD_ENABLE	0x0010

/* LCD Panel Configuration Register (LCCR)	0x0840 */

#define LCD_IEN		0x00008000	/* LCD interrupt enable */
#define LCD_CLKP	0x00000800	/* LCD Clock Polarity */
#define LCD_OEP		0x00000400	/* LCD Output Enable Polarity */
#define LCD_HSP		0x00000200	/* LCD horizontal sync polarity */
#define LCD_VSP		0x00000100	/* LCD vertical sync polarity */
#define LCD_DP		0x00000080	/* LCD data polarity */
#define LCD_BPIX	0x00000060	/* LCD bits per pixel mask */
#define LCD_BPIX_8	0x00000060	/* eight bits per pixel setting */
#define LCD_BPIX_4	0x00000040	/* four bits per pixel setting */
#define LCD_BPIX_2	0x00000020	/* two bits per pixel setting */
#define LCD_BPIX_1	0x00000000	/* one bit per pixel setting */
#define LCD_LBW		0x00000010	/* LCD Bus width */
#define LCD_LBW_8	0x00000010	/* LCD Bus width 8 */
#define LCD_LBW_4	0x00000000	/* LCD Bus width 4 */
#define LCD_SPLT	0x00000008	/* LCD split display mode */
#define LCD_CLOR	0x00000004	/* LCD color display */
#define LCD_TFT		0x00000002	/* LCD TFT display */
#define LCD_PON		0x00000001	/* Panel On/Off control bit */

#ifdef  __cplusplus
}
#endif

#endif /* __INCppc860Siuh */