ppc860siu.h

这是motorola公司的powerpc芯片上的嵌入式linux上的驱动程序和测试程序

#define PSMR3(base)	(CAST(VUINT16 *)((base) + 0x0A48)) /* SCC3 Proto Spec */
#define TODR3(base)	(CAST(VUINT16 *)((base) + 0x0A4C)) /* SCC3 Tx Demand*/
#define DSR3(base)	(CAST(VUINT16 *)((base) + 0x0A4E)) /* SCC3 Data Sync */
#define SCCE3(base)	(CAST(VUINT16 *)((base) + 0x0A50)) /* SCC3 Event Reg */
#define SCCM3(base)	(CAST(VUINT16 *)((base) + 0x0A54)) /* SCC3 Mask Reg */
#define SCCS3(base)	(CAST(VUINT8 *) ((base) + 0x0A57)) /* SCC3 Status Reg */

/* SCC 4 register set */

#define GSMR_L4(base)	(CAST(VUINT32 *)((base) + 0x0A60)) /* SCC4 Gen Mode*/
#define GSMR_H4(base)	(CAST(VUINT32 *)((base) + 0x0A64)) /* SCC4 Gen Mode*/
#define PSMR4(base)	(CAST(VUINT16 *)((base) + 0x0A68)) /* SCC4 Proto Spec */
#define TODR4(base)	(CAST(VUINT16 *)((base) + 0x0A6C)) /* SCC4 Tx Demand*/
#define DSR4(base)	(CAST(VUINT16 *)((base) + 0x0A6E)) /* SCC4 Data Sync */
#define SCCE4(base)	(CAST(VUINT16 *)((base) + 0x0A70)) /* SCC4 Event Reg */
#define SCCM4(base)	(CAST(VUINT16 *)((base) + 0x0A74)) /* SCC2 Mask Reg */
#define SCCS4(base)	(CAST(VUINT8 *) ((base) + 0x0A77)) /* SCC4 Status Reg */

/* SMC 1 register set */

#define	SMCMR1(base)	(CAST(VUINT16 *)((base) + 0x0A82)) /* SMC1 Mode Reg */
#define	SMCE1(base)	(CAST(VUINT8 *) ((base) + 0x0A86)) /* SMC1 Event Reg */
#define	SMCM1(base)	(CAST(VUINT8 *) ((base) + 0x0A8A)) /* SMC1 Mask Reg */

/* SMC 2 register set */

#define	SMCMR2(base)	(CAST(VUINT16 *)((base) + 0x0A92)) /* SMC2 Mode Reg */
#define	SMCE2(base)	(CAST(VUINT8 *) ((base) + 0x0A96)) /* SMC2/PIP Event*/
#define	SMCM2(base)	(CAST(VUINT8 *) ((base) + 0x0A9A)) /* SMC2 Mask Reg */

/* SPI regiter set */

#define	SPMODE(base)	(CAST(VUINT16 *)((base) + 0x0AA0)) /* SPI Mode Reg */
#define	SPIE(base)	(CAST(VUINT8 *) ((base) + 0x0AA6)) /* SPI Event Reg */
#define	SPIM(base)	(CAST(VUINT8 *) ((base) + 0x0AAA)) /* SPI Mask Reg */
#define	SPCOM(base)	(CAST(VUINT8 *) ((base) + 0x0AAD)) /* SPI Command Reg */

/* PIP register set */

#define	PIPC(base)	(CAST(VUINT16 *)((base) + 0x0AB2)) /* PIP Config Reg */
#define	PTPR(base)	(CAST(VUINT16 *)((base) + 0x0AB6)) /* PIP Timing parms*/
#define	PBDIR(base)	(CAST(VUINT32 *)((base) + 0x0AB8)) /* PB data dir */
#define	PBPAR(base)	(CAST(VUINT32 *)((base) + 0x0ABC)) /* PB pin ass*/
#define	PBODR(base)	(CAST(VUINT16 *)((base) + 0x0AC2)) /* PB open drain*/
#define	PBDAT(base)	(CAST(VUINT32 *)((base) + 0x0AC4)) /* PB Data Reg*/

/* SI register set */

#define	SIMODE(base)	(CAST(VUINT32 *)((base) + 0x0AE0)) /* SI Mode Reg */
#define	SIGMR(base)	(CAST(VUINT8 *) ((base) + 0x0AE4)) /* SI Global Mode */
#define	SISTR(base)	(CAST(VUINT8 *) ((base) + 0x0AE6)) /* SI Status Reg */
#define	SICMR(base)	(CAST(VUINT8 *) ((base) + 0x0AE7)) /* SI Command Reg */
#define	SICR(base)	(CAST(VUINT32 *)((base) + 0x0AEC)) /* SI Clock route */
#define	SIRP(base)	(CAST(VUINT32 *) ((base) + 0x0AF0)) /* SI RAM pointers*/
#define	SIRAM(base)	(CAST(VUINT32 *)((base) + 0x0C00)) /* SI Routing RAM */

#define MPC860_REGB_OFFSET      0x2000  /* offset to internal registers */
 
/* Data Param RAM */

#define       DPRAM(base)     (CAST(VUINT32 *) ((base) + MPC860_REGB_OFFSET))

/* MPC860 Dual Ported Ram addresses */
 
#define MPC860_DPR_SCC1(base)  (CAST(VUINT32 *) ((base) + MPC860_REGB_OFFSET \
                                                 + 0x1c00))

/* SIU Module Configuration register bit definition (SIUMCR - 0x00) */

#define SIUMCR_EARB		0x80000000	/* External Abritation */
#define SIUMCR_EARP		0x70000000	/* Extern Abri. Request prior.*/
#define SIUMCR_DSHW		0x00800000	/* Data Showcycles */
#define SIUMCR_DBGC		0x00600000	/* Debug pins configuration */
#define SIUMCR_DBPC		0x00180000	/* Debug Port pins Config. */
#define SIUMCR_FRC		0x00020000	/* FRZ pin Configuration */
#define SIUMCR_DLK		0x00010000	/* Debug Register Lock */
#define SIUMCR_PNCS		0x00008000	/* Parity Non-mem Crtl reg */
#define SIUMCR_OPAR		0x00004000	/* Odd Parity */
#define SIUMCR_DPC		0x00002000	/* Data Parity pins Config. */
#define SIUMCR_MPRE		0x00001000	/* Multi CPU Reserva. Enable */
#define SIUMCR_MLRC_IRQ4	0x00000000	/* Multi Level Reserva. Ctrl */
#define SIUMCR_MLRC_3STATES	0x00000400	/* Multi Level Reserva. Ctrl */
#define SIUMCR_MLRC_KR		0x00000800	/* Multi Level Reserva. Ctrl */
#define SIUMCR_MLRC_SPK	ROUT	0x00000c00	/* Multi Level Reserva. Ctrl */
#define SIUMCR_AEME		0x00000200	/* Asynchro External Master */
#define SIUMCR_SEME		0x00000100	/* Synchro External Master */
#define SIUMCR_BSC		0x00000080	/* Byte Select Configuration */
#define SIUMCR_GB5E		0x00000040	/* GPL_B(5) Enable */
#define SIUMCR_B2DD		0x00000020	/* Bank 2 Double Drive */
#define SIUMCR_B3DD		0x00000010	/* Bank 3 Double Drive */

/* System Portection Control register bit definition (SYPCR - 0x04) */

#define SYPCR_SWTC	0xffff0000	/* Software Watchdog Timer Count */
#define SYPCR_BMT	0x0000ff00	/* Bus Monitor Timing */
#define SYPCR_BME	0x00000080	/* Bus Monitor Enable */
#define SYPCR_SWF	0x00000008	/* Software Watchdog Freeze */
#define SYPCR_SWE	0x00000004	/* Software Watchdog Enable */
#define SYPCR_SWRI	0x00000002	/* Software Watchdog Reset/Int Select */
#define SYPCR_SWP	0x00000001	/* Software Watchdog Prescale */

/* System Interrupt PENDing register bit definition (SIPEND - 0x10) */

#define SIPEND_IRQ0	0x80000000	/* Interrupt IRQ0 pending */
#define SIPEND_LVL0	0x40000000	/* Interrupt LEVEL 0 pending */
#define SIPEND_IRQ1	0x20000000	/* Interrupt IRQ1 pending */
#define SIPEND_LVL1	0x10000000	/* Interrupt LEVEL 1 pending */
#define SIPEND_IRQ2	0x08000000	/* Interrupt IRQ2 pending */
#define SIPEND_LVL2	0x04000000	/* Interrupt LEVEL 2 pending */
#define SIPEND_IRQ3	0x02000000	/* Interrupt IRQ3 pending */
#define SIPEND_LVL3	0x01000000	/* Interrupt LEVEL 3 pending */
#define SIPEND_IRQ4	0x00800000	/* Interrupt IRQ4 pending */
#define SIPEND_LVL4	0x00400000	/* Interrupt LEVEL 4 pending */
#define SIPEND_IRQ5	0x00200000	/* Interrupt IRQ5 pending */
#define SIPEND_LVL5	0x00100000	/* Interrupt LEVEL 5 pending */
#define SIPEND_IRQ6	0x00080000	/* Interrupt IRQ6 pending */
#define SIPEND_LVL6	0x00040000	/* Interrupt LEVEL 6 pending */
#define SIPEND_IRQ7	0x00020000	/* Interrupt IRQ7 pending */
#define SIPEND_LVL7	0x00010000	/* Interrupt LEVEL 7 pending */

/* System Interrupt MASK register bit definition (SIMARK - 0x14) */

#define SIMASK_IRM0	0x80000000	/* Interrupt IRQ0 mask */
#define SIMASK_LVM0	0x40000000	/* Interrupt LEVEL 0 mask */
#define SIMASK_IRM1	0x20000000	/* Interrupt IRQ1 mask */
#define SIMASK_LVM1	0x10000000	/* Interrupt LEVEL 1 mask */
#define SIMASK_IRM2	0x08000000	/* Interrupt IRQ2 mask */
#define SIMASK_LVM2	0x04000000	/* Interrupt LEVEL 2 mask */
#define SIMASK_IRM3	0x02000000	/* Interrupt IRQ3 mask */
#define SIMASK_LVM3	0x01000000	/* Interrupt LEVEL 3 mask */
#define SIMASK_IRM4	0x00800000	/* Interrupt IRQ4 mask */
#define SIMASK_LVM4	0x00400000	/* Interrupt LEVEL 4 mask */
#define SIMASK_IRM5	0x00200000	/* Interrupt IRQ5 mask */
#define SIMASK_LVM5	0x00100000	/* Interrupt LEVEL 5 mask */
#define SIMASK_IRM6	0x00080000	/* Interrupt IRQ6 mask */
#define SIMASK_LVM6	0x00040000	/* Interrupt LEVEL 6 mask */
#define SIMASK_IRM7	0x00020000	/* Interrupt IRQ7 mask */
#define SIMASK_LVM7	0x00010000	/* Interrupt LEVEL 7 mask */
#define SIMASK_ALL	0xffff0000	/* All interrupt mask */

/* System Interrupt Edge Level mask register bit definition (SIEL - 0x1C) */

#define SIEL_ED0	0x80000000	/* Interrupt IRQ0 on falling Edge */
#define SIEL_WM0	0x40000000	/* Interrupt IRQ0 Wake up Mask */
#define SIEL_ED1	0x20000000	/* Interrupt IRQ1 on falling Edge */
#define SIEL_WM1	0x10000000	/* Interrupt IRQ1 Wake up Mask */
#define SIEL_ED2	0x08000000	/* Interrupt IRQ2 on falling Edge */
#define SIEL_WM2	0x04000000	/* Interrupt IRQ2 Wake up Mask */
#define SIEL_ED3	0x02000000	/* Interrupt IRQ3 on falling Edge */
#define SIEL_WM3	0x01000000	/* Interrupt IRQ3 Wake up Mask */
#define SIEL_ED4	0x00800000	/* Interrupt IRQ4 on falling Edge */
#define SIEL_WM4	0x00400000	/* Interrupt IRQ4 Wake up Mask */
#define SIEL_ED5	0x00200000	/* Interrupt IRQ5 on falling Edge */
#define SIEL_WM5	0x00100000	/* Interrupt IRQ5 Wake up Mask */
#define SIEL_ED6	0x00080000	/* Interrupt IRQ6 on falling Edge */
#define SIEL_WM6	0x00040000	/* Interrupt IRQ6 Wake up Mask */
#define SIEL_ED7	0x00020000	/* Interrupt IRQ7 on falling Edge */
#define SIEL_WM7	0x00010000	/* Interrupt IRQ7 Wake up Mask */

/* Transfert Error Status register bit definition (TESR - 0x20) */

#define TESR_IEXT	0x00002000	/* Instr. External Transfer Error Ack */
#define TESR_IBM	0x00001000	/* Instr. transfer Monitor Time-Out */
#define TESR_IPB	0x00000f00	/* Instr. Parity Error on Byte */
#define TESR_DEXT	0x00000020	/* Data External Transfer Error Ack */
#define TESR_DBM	0x00000010	/* Data transfer Monitor Time-Out */
#define TESR_DPB	0x0000000f	/* Data Parity Error on Byte */

/* Memory STATus register bit definition (MSTAT - 0x178) */

#define MSTAT_PER0	0x8000		/* Parity Error bank 0 */
#define MSTAT_PER1	0x4000		/* Parity Error bank 1 */
#define MSTAT_PER2	0x2000		/* Parity Error bank 2 */
#define MSTAT_PER3	0x1000		/* Parity Error bank 3 */
#define MSTAT_PER4	0x0800		/* Parity Error bank 4 */
#define MSTAT_PER5	0x0400		/* Parity Error bank 5 */
#define MSTAT_PER6	0x0200		/* Parity Error bank 6 */
#define MSTAT_PER7	0x0100		/* Parity Error bank 7 */
#define MSTAT_WPER	0x0080		/* Write Protection Error */

/* Memory Periodic Timer Prescaler Register bit definition (MPTPR - 0x17A) */

#define MPTPR_PTP_MSK	0xff00		/* Periodic Timers Prescaler Mask */
#define MPTPR_PTP_DIV2	0x2000		/* BRGCLK divided by 2 */
#define MPTPR_PTP_DIV4	0x1000		/* BRGCLK divided by 4 */
#define MPTPR_PTP_DIV8	0x0800		/* BRGCLK divided by 8 */
#define MPTPR_PTP_DIV16	0x0400		/* BRGCLK divided by 16 */
#define MPTPR_PTP_DIV32	0x0200		/* BRGCLK divided by 32 */
#define MPTPR_PTP_DIV64	0x0100		/* BRGCLK divided by 64 */

/* Base Register bit definition (BRx - 0x100) */

#define BR_BA_MSK	0xffff8000	/* Base Address Mask */
#define BR_AT_MSK	0x00007000	/* Address Type Mask */
#define BR_PS_MSK	0x00000c00	/* Port Size Mask */
#define BR_PARE		0x00000200	/* Parity Enable */
#define BR_WP		0x00000100	/* Write Protect */
#define BR_MS_MSK	0x000000c0	/* Machine Select Mask */
#define BR_MS_GPCM	0x00000000	/* G.P.C.M. Machine Select */
#define BR_MS_UPMA	0x00000080	/* U.P.M.A Machine Select */
#define BR_MS_UPMB	0x000000c0	/* U.P.M.B Machine Select */
#define BR_V		0x00000001	/* Bank Valid */
#define BR_PS_8		0x00000400	/* 8 bit port size */
#define BR_PS_16	0x00000800	/* 16 bit port size */
#define BR_PS_32	0x00000000	/* 32 bit port size */

/* Option Register bit definition (ORx - 0x104) */

#define OR_AM_MSK	0xffff8000	/* Address Mask Mask */
#define OR_ATM_MSK	0x00007000	/* Address Type Mask Mask */
#define OR_CSNT_SAM	0x00000800	/* Chip Select Negation Time/ Start */
					/* Address Multiplex */
#define OR_ACS_MSK	0x00000600	/* Address to Chip Select Setup mask */
#define OR_ACS_DIV1	0x00000000	/* CS is output at the same time */
#define OR_ACS_DIV4	0x00000400	/* CS is output 1/4 a clock later */
#define OR_ACS_DIV2	0x00000600	/* CS is output 1/2 a clock later */
#define OR_BI		0x00000100	/* Burst inhibit */
#define OR_SCY_MSK	0x000000f0	/* Cycle Lenght in Clocks */
#define OR_SCY_0_CLK	0x00000000	/* 0 clock cycles wait states */
#define OR_SCY_1_CLK	0x00000010	/* 1 clock cycles wait states */
#define OR_SCY_2_CLK	0x00000020	/* 2 clock cycles wait states */
#define OR_SCY_3_CLK	0x00000030	/* 3 clock cycles wait states */
#define OR_SCY_4_CLK	0x00000040	/* 4 clock cycles wait states */
#define OR_SCY_5_CLK	0x00000050	/* 5 clock cycles wait states */
#define OR_SCY_6_CLK	0x00000060	/* 6 clock cycles wait states */
#define OR_SCY_7_CLK	0x00000070	/* 7 clock cycles wait states */
#define OR_SCY_8_CLK	0x00000080	/* 8 clock cycles wait states */
#define OR_SCY_9_CLK	0x00000090	/* 9 clock cycles wait states */
#define OR_SCY_10_CLK	0x000000a0	/* 10 clock cycles wait states */
#define OR_SCY_11_CLK	0x000000b0	/* 11 clock cycles wait states */
#define OR_SCY_12_CLK	0x000000c0	/* 12 clock cycles wait states */
#define OR_SCY_13_CLK	0x000000d0	/* 13 clock cycles wait states */
#define OR_SCY_14_CLK	0x000000e0	/* 14 clock cycles wait states */
#define OR_SCY_15_CLK	0x000000f0	/* 15 clock cycles wait states */
#define OR_SETA		0x00000008	/* External Transfer Acknowledge */
#define OR_TRLX		0x00000004	/* Timing Relaxed */

/* Memory Command Register bit definition (MCR - 0x168) */

#define MCR_OP_WRITE	0x00000000	/* Command Opcode: Write */
#define MCR_OP_READ	0x40000000	/* Command Opcode: Read */
#define MCR_OP_RUN	0x80000000	/* Command Opcode: Run */
#define MCR_UM_MSK	0x00800000	/* User Machine mask */
#define MCR_UM_UPMA	0x00000000	/* User Machine = UPMA */
#define MCR_UM_UPMB	0x00800000	/* User Machine = UPMB */
#define MCR_MB_MSK	0x0000e000	/* Memory Bank mask */
#define MCR_MB_CS0	0x00000000	/* CS0 enabled */
#define MCR_MB_CS1	0x00002000	/* CS1 enabled */
#define MCR_MB_CS2	0x00004000	/* CS3 enabled */
#define MCR_MB_CS3	0x00006000	/* CS3 enabled */
#define MCR_MB_CS4	0x00008000	/* CS4 enabled */
#define MCR_MB_CS5	0x0000a000	/* CS5 enabled */
#define MCR_MB_CS6	0x0000c000	/* CS6 enabled */
#define MCR_MB_CS7	0x0000e000	/* CS7 enabled */
#define MCR_MCLF_MSK	0x00000f00	/* Memory Command Loop Field mask */
#define MCR_MCLF_1X	0x00000100	/* The Cmd Loop is executed 1 time */
#define MCR_MCLF_2X	0x00000200	/* The Cmd Loop is executed 2 times */
#define MCR_MCLF_3X	0x00000300	/* The Cmd Loop is executed 3 times */
#define MCR_MCLF_4X	0x00000400	/* The Cmd Loop is executed 4 times */
#define MCR_MCLF_5X	0x00000500	/* The Cmd Loop is executed 5 times */
#define MCR_MCLF_6X	0x00000600	/* The Cmd Loop is executed 6 times */
#define MCR_MCLF_7X	0x00000700	/* The Cmd Loop is executed 7 times */
#define MCR_MCLF_8X	0x00000800	/* The Cmd Loop is executed 8 times */
#define MCR_MCLF_9X	0x00000900	/* The Cmd Loop is executed 9 times */
#define MCR_MCLF_10X	0x00000a00	/* The Cmd Loop is executed 10 times */
#define MCR_MCLF_11X	0x00000b00	/* The Cmd Loop is executed 11 times */