ppc860siu.h

这是motorola公司的powerpc芯片上的嵌入式linux上的驱动程序和测试程序

/* ppc860Siu.h - Motorola System Interface Unit header file */

/*
This file contains constants of the System Interface Unit (SIU) for the
Motorola MPC860 and MPC821 PowerPC microcontroller
*/

#ifndef __INCppc860Siuh
#define __INCppc860Siuh

#ifdef __cplusplus
extern "C" {
#endif

#ifdef	_ASMLANGUAGE
#define CAST(x)
#else /* _ASMLANGUAGE */
typedef volatile UCHAR  VCHAR;   /* shorthand for volatile UCHAR */
typedef volatile INT32  VINT32; /* volatile unsigned word */
typedef volatile INT16  VINT16; /* volatile unsigned halfword */
typedef volatile INT8   VINT8;   /* volatile unsigned byte */
typedef volatile UINT32 VUINT32; /* volatile unsigned word */
typedef volatile UINT16 VUINT16; /* volatile unsigned halfword */
typedef volatile UINT8  VUINT8;   /* volatile unsigned byte */
#define CAST(x) (x)
#endif	/* _ASMLANGUAGE */


/* 
 * MPC860/MPC821 internal register/memory map (section 17 of prelim. spec)
 * note that these are offsets from the value stored in the IMMR 
 * register, which is in the PowerPC special register address space
 * at register number 638
 */

/* General SIU registers */

#define SIUMCR(base)	(CAST(VUINT32 *)((base) + 0x0000)) /* SIU Module Conf*/
#define	SYPCR(base)	(CAST(VUINT32 *)((base) + 0x0004)) /* Protection Ctrl */
#define	SWT(base)	(CAST(VUINT32 *)((base) + 0x0008)) /* SW watch dog */
#define	SWSR(base)	(CAST(VUINT16 *)((base) + 0x000E)) /* SW Service Reg */
#define	SIPEND(base)	(CAST(VUINT32 *)((base) + 0x0010)) /* Intr Pending reg*/
#define	SIMASK(base)	(CAST(VUINT32 *)((base) + 0x0014)) /* Intr Mask reg */
#define	SIEL(base)	(CAST(VUINT32 *)((base) + 0x0018)) /* Intr Edge Lvl */
#define	SIVEC(base)	(CAST(VUINT32 *)((base) + 0x001C)) /* Intr Vector reg */
#define	TESR(base)	(CAST(VUINT32 *)((base) + 0x0020)) /* Tx Error Status */
#define	SDCR(base)	(CAST(VUINT32 *)((base) + 0x0030)) /* SDMA Config Reg */

/* PCMCIA registers */

#define PBR0(base)	(CAST(VUINT32 *)((base) + 0x0080)) /* PCMCIA base 0 */
#define POR0(base)	(CAST(VUINT32 *)((base) + 0x0084)) /* PCMCIA option 0 */
#define PBR1(base)	(CAST(VUINT32 *)((base) + 0x0088)) /* PCMCIA base 1 */
#define POR1(base)	(CAST(VUINT32 *)((base) + 0x008C)) /* PCMCIA option 1 */
#define PBR2(base)	(CAST(VUINT32 *)((base) + 0x0090)) /* PCMCIA base 2 */
#define POR2(base)	(CAST(VUINT32 *)((base) + 0x0094)) /* PCMCIA option 2 */
#define PBR3(base)	(CAST(VUINT32 *)((base) + 0x0098)) /* PCMCIA base 3 */
#define POR3(base)	(CAST(VUINT32 *)((base) + 0x009C)) /* PCMCIA option 3 */
#define PBR4(base)	(CAST(VUINT32 *)((base) + 0x00A0)) /* PCMCIA base 4 */
#define POR4(base)	(CAST(VUINT32 *)((base) + 0x00A4)) /* PCMCIA option 4 */
#define PBR5(base)	(CAST(VUINT32 *)((base) + 0x00A8)) /* PCMCIA base 5 */
#define POR5(base)	(CAST(VUINT32 *)((base) + 0x00AC)) /* PCMCIA option 5 */
#define PBR6(base)	(CAST(VUINT32 *)((base) + 0x00B0)) /* PCMCIA base 6 */
#define POR6(base)	(CAST(VUINT32 *)((base) + 0x00B4)) /* PCMCIA option 6 */
#define PBR7(base)	(CAST(VUINT32 *)((base) + 0x00B8)) /* PCMCIA base 7 */
#define POR7(base)	(CAST(VUINT32 *)((base) + 0x00BC)) /* PCMCIA option 7 */

#define PGCRA(base)	(CAST(VUINT32 *)((base) + 0x00E0)) /* slot A ctrl */
#define PGCRB(base)	(CAST(VUINT32 *)((base) + 0x00E4)) /* slot B ctrl */
#define PSCR(base)	(CAST(VUINT32 *)((base) + 0x00E8)) /* PCMCIA Status */
#define PIPR(base)	(CAST(VUINT32 *)((base) + 0x00F0)) /* pins value */
#define PER(base)	(CAST(VUINT32 *)((base) + 0x00f8)) /* PCMCIA Enable */

/* MEMC registers */

#define BR0(base)	(CAST(VUINT32 *)((base) + 0x0100)) /* Base Reg bank 0 */
#define OR0(base)	(CAST(VUINT32 *)((base) + 0x0104)) /* Opt Reg bank 0*/
#define BR1(base)	(CAST(VUINT32 *)((base) + 0x0108)) /* Base Reg bank 1 */
#define OR1(base)	(CAST(VUINT32 *)((base) + 0x010C)) /* Opt Reg bank 1*/
#define BR2(base)	(CAST(VUINT32 *)((base) + 0x0110)) /* Base Reg bank 2 */
#define OR2(base)	(CAST(VUINT32 *)((base) + 0x0114)) /* Opt Reg bank 2*/
#define BR3(base)	(CAST(VUINT32 *)((base) + 0x0118)) /* Base Reg bank 3 */
#define OR3(base)	(CAST(VUINT32 *)((base) + 0x011C)) /* Opt Reg bank 3*/
#define BR4(base)	(CAST(VUINT32 *)((base) + 0x0120)) /* Base Reg bank 4 */
#define OR4(base)	(CAST(VUINT32 *)((base) + 0x0124)) /* Opt Reg bank 4*/
#define BR5(base)	(CAST(VUINT32 *)((base) + 0x0128)) /* Base Reg bank 5 */
#define OR5(base)	(CAST(VUINT32 *)((base) + 0x012C)) /* Opt Reg bank 5*/
#define BR6(base)	(CAST(VUINT32 *)((base) + 0x0130)) /* Base Reg bank 6 */
#define OR6(base)	(CAST(VUINT32 *)((base) + 0x0134)) /* Opt Reg bank 6*/
#define BR7(base)	(CAST(VUINT32 *)((base) + 0x0138)) /* Base Reg bank 7 */
#define OR7(base)	(CAST(VUINT32 *)((base) + 0x013C)) /* Opt Reg bank 7*/

#define MAR(base)	(CAST(VUINT32 *)((base) + 0x0164)) /* Memory Address */
#define MCR(base)	(CAST(VUINT32 *)((base) + 0x0168)) /* Memory Command */
#define MAMR(base)	(CAST(VUINT32 *)((base) + 0x0170)) /* Machine A Mode */
#define MBMR(base)	(CAST(VUINT32 *)((base) + 0x0174)) /* Machine B Mode */
#define MSTAT(base)	(CAST(VUINT16 *)((base) + 0x0178)) /* Memory Status */
#define MPTPR(base)	(CAST(VUINT16 *)((base) + 0x017A)) /* Mem Timer Presc*/
#define MDR(base)	(CAST(VUINT32 *)((base) + 0x017C)) /* Memory Data */

/* System Integration Timers */

#define TBSCR(base)	(CAST(VUINT16 *)((base) + 0x0200)) /* T.B. Status Ctrl*/
#define TBREFF0(base)	(CAST(VUINT32 *)((base) + 0x0204)) /* Time Base Ref 0 */
#define TBREFF1(base)	(CAST(VUINT32 *)((base) + 0x0208)) /* Time Base Ref 1 */

#define RTCSC(base)	(CAST(VUINT16 *)((base) + 0x0220)) /* Clock Stat Ctrl*/
#define RTC(base)	(CAST(VUINT32 *)((base) + 0x0224)) /* RT Clock */
#define RTSEC(base)	(CAST(VUINT32 *)((base) + 0x0228)) /* RT Alarm Seconds*/
#define RTCAL(base)	(CAST(VUINT32 *)((base) + 0x022C)) /* Real Time Alarm */

#define PISCR(base)	(CAST(VUINT16 *)((base) + 0x0240)) /* PIT Status Ctrl */
#define PITC(base)	(CAST(VUINT32 *)((base) + 0x0244)) /* PIT Count */
#define PITR(base)	(CAST(VUINT32 *)((base) + 0x0248)) /* PIT */

/* Clock and Reset */

#define SCCR(base)	(CAST(VUINT32 *)((base) + 0x0280)) /* Sys Clock Ctrl*/
#define PLPRCR(base)	(CAST(VUINT32 *)((base) + 0x0284)) /* PLL LPower Reset*/
#define RSR(base)	(CAST(VUINT32 *)((base) + 0x0288)) /* Reset Status Reg*/

/* System Integration Timers Keys */

#define TBSCRK(base)	(CAST(VUINT32 *)((base) + 0x0300)) /* TB Stat Ctrl key*/
#define TBREFF0K(base)	(CAST(VUINT32 *)((base) + 0x0304)) /* TB Ref 0 Key */
#define TBREFF1K(base)	(CAST(VUINT32 *)((base) + 0x0308)) /* TB Ref 1 Key */
#define TBK(base)	(CAST(VUINT32 *)((base) + 0x030C)) /* TB & Dec Key */

#define RTCSCK(base)	(CAST(VUINT32 *)((base) + 0x0320)) /* RT Stat Ctrl Key*/
#define RTCK(base)	(CAST(VUINT32 *)((base) + 0x0324)) /* RT Clock Key */
#define RTSECK(base)	(CAST(VUINT32 *)((base) + 0x0328)) /* RT Alarm Second */
#define RTCALK(base)	(CAST(VUINT32 *)((base) + 0x032C)) /* R T Alarm Key */

#define PISCRK(base)	(CAST(VUINT32 *)((base) + 0x0340)) /* PIT Stat Ctrl Key*/
#define PITCK(base)	(CAST(VUINT32 *)((base) + 0x0344)) /* PIT Count Key */

/* Clock and Reset Keys */

#define SCCRK(base)	(CAST(VUINT32 *)((base) + 0x0380)) /* System Clk Ctrl */
#define PLPRCRK(base)	(CAST(VUINT32 *)((base) + 0x0384)) /* Pll, LP&R Ctrl */
#define RSRK(base)	(CAST(VUINT32 *)((base) + 0x0388)) /* Reset Status Key*/

/* LCD */

#define LCOLR(base)	(CAST(VUINT16 *)((base) + 0x0E00)) /* Color Ram */
#define LCCR(base)	(CAST(VUINT32 *)((base) + 0x0840)) /* Config reg */
#define LCHCR(base)	(CAST(VUINT32 *)((base) + 0x0844)) /* Horizontal */
#define LCVCR(base)	(CAST(VUINT32 *)((base) + 0x0848)) /* Vertical */
#define LCFAA(base)	(CAST(VUINT32 *)((base) + 0x0850)) /* Frame A buf */
#define LCFBA(base)	(CAST(VUINT32 *)((base) + 0x0854)) /* Frame B buf */
#define LCSR(base)	(CAST(VUINT8 *) ((base) + 0x0858)) /* Status reg */

/* I2C */

#define I2MOD(base)	(CAST(VUINT8 *)((base) + 0x0860)) /* I2C Mode register*/
#define I2ADD(base)	(CAST(VUINT8 *)((base) + 0x0864)) /* I2C Address reg */
#define I2BRG(base)	(CAST(VUINT8 *)((base) + 0x0868)) /* I2C BRG register */
#define I2COM(base)	(CAST(VUINT8 *)((base) + 0x086C)) /* I2C Command reg */
#define I2CER(base)	(CAST(VUINT8 *)((base) + 0x0870)) /* I2C Event Reg */
#define I2CMR(base)	(CAST(VUINT8 *)((base) + 0x0874)) /* I2C Mask Reg */

/* DMA */

#define SDAR(base)	(CAST(VUINT32 *)((base) + 0x0904)) /* SDMA Address Reg*/
#define SDSR(base)	(CAST(VUINT8 *)((base) + 0x0908)) /* SDMA Status Reg */
#define SDMR(base)	(CAST(VUINT8 *)((base) + 0x090C)) /* SDMA Mask Reg */
#define IDSR1(base)	(CAST(VUINT8 *)((base) + 0x0910)) /* IDMA 1 Status Reg*/
#define IDMR1(base)	(CAST(VUINT8 *)((base) + 0x0914)) /* IDMA 1 Mask Reg */
#define IDSR2(base)	(CAST(VUINT8 *)((base) + 0x0918)) /* IDMA 2 Status Reg*/
#define IDMR2(base)	(CAST(VUINT8 *)((base) + 0x091C)) /* IDMA 2 Mask Reg */

/* CPM Interrupt Control registers */

#define	CIVR(base)	(CAST(VUINT16 *)((base) + 0x0930)) /* CP Int vector */
#define	CICR(base)	(CAST(VUINT32 *)((base) + 0x0940)) /* CP Int config */
#define	CIPR(base)	(CAST(VUINT32 *)((base) + 0x0944)) /* CP Int pending */
#define	CIMR(base)	(CAST(VUINT32 *)((base) + 0x0948)) /* CP Int mask reg */
#define	CISR(base)	(CAST(VUINT32 *)((base) + 0x094C)) /* CP Int in-serv*/

/* Input/Output Port register */

#define	PADIR(base)	(CAST(VUINT16 *)((base) + 0x0950)) /* PA data dir*/
#define	PAPAR(base)	(CAST(VUINT16 *)((base) + 0x0952)) /* PA pin assign*/
#define	PAODR(base)	(CAST(VUINT16 *)((base) + 0x0954)) /* PA open drain*/
#define	PADAT(base)	(CAST(VUINT16 *)((base) + 0x0956)) /* PA data reg */
#define	PCDIR(base)	(CAST(VUINT16 *)((base) + 0x0960)) /* PC data dir */
#define	PCPAR(base)	(CAST(VUINT16 *)((base) + 0x0962)) /* PC pin assign*/
#define	PCSO(base)	(CAST(VUINT16 *)((base) + 0x0964)) /* PC options */
#define	PCDAT(base)	(CAST(VUINT16 *)((base) + 0x0966)) /* PC data reg */
#define	PCINT(base)	(CAST(VUINT16 *)((base) + 0x0968)) /* PC intr ctrl */
#define	PDDIR(base)	(CAST(VUINT16 *)((base) + 0x0970)) /* PD data dir */
#define	PDPAR(base)	(CAST(VUINT16 *)((base) + 0x0972)) /* PD pin assign*/
#define	PDDAT(base)	(CAST(VUINT16 *)((base) + 0x0976)) /* PD data reg */

/* CPM timer register set */

#define TGCR(base)	(CAST(VUINT16 *)((base) + 0x0980)) /* Tmr Global Cfg */
#define TMR1(base)	(CAST(VUINT16 *)((base) + 0x0990)) /* Tmr 1 Mode Reg */
#define TMR2(base)	(CAST(VUINT16 *)((base) + 0x0992)) /* Tmr 2 Mode Reg */
#define TRR1(base)	(CAST(VUINT16 *)((base) + 0x0994)) /* Tmr 1 Ref Reg */
#define TRR2(base)	(CAST(VUINT16 *)((base) + 0x0996)) /* Tmr 2 Ref Reg */
#define TCR1(base)	(CAST(VUINT16 *)((base) + 0x0998)) /* Tmr 1 Capture */
#define TCR2(base)	(CAST(VUINT16 *)((base) + 0x099A)) /* Tmr 2 Capture */
#define TCN1(base)	(CAST(VUINT16 *)((base) + 0x099C)) /* Tmr 1 Counter */
#define TCN2(base)	(CAST(VUINT16 *)((base) + 0x099E)) /* Tmr 2 Counter */

#define TMR3(base)	(CAST(VUINT16 *)((base) + 0x09A0)) /* Tmr 3 Mode Reg */
#define TMR4(base)	(CAST(VUINT16 *)((base) + 0x09A2)) /* Tmr 4 Mode Reg */
#define TRR3(base)	(CAST(VUINT16 *)((base) + 0x09A4)) /* Tmr 3 Reference*/
#define TRR4(base)	(CAST(VUINT16 *)((base) + 0x09A6)) /* Tmr 4 Reference*/
#define TCR3(base)	(CAST(VUINT16 *)((base) + 0x09A8)) /* Tmr 3 Capture */
#define TCR4(base)	(CAST(VUINT16 *)((base) + 0x09AA)) /* Tmr 4 Capture */
#define TCN3(base)	(CAST(VUINT16 *)((base) + 0x09AC)) /* Tmr 3 Counter */
#define TCN4(base)	(CAST(VUINT16 *)((base) + 0x09AE)) /* Tmr 4 Counter */

#define TER1(base)	(CAST(VUINT16 *)((base) + 0x09B0)) /* Tmr 1 Event */
#define TER2(base)	(CAST(VUINT16 *)((base) + 0x09B2)) /* Tmr 2 Event */
#define TER3(base)	(CAST(VUINT16 *)((base) + 0x09B4)) /* Tmr 3 Event */
#define TER4(base)	(CAST(VUINT16 *)((base) + 0x09B6)) /* Tmr 4 Event */

/* Communication Processor register set */

#define	CPCR(base)	(CAST(VUINT16 *)((base) + 0x09C0)) /* Com Proc Cmd*/
#define	RCCR(base)	(CAST(VUINT16 *)((base) + 0x09C4)) /* RISC Config Reg */
#define	RMDS(base)	(CAST(VUINT8 *) ((base) + 0x09C7)) /* RISC Dev Sup stat*/
#define	RMDR(base)	(CAST(VUINT32 *)((base) + 0x09C8)) /* Mcode Dev ctrl */
#define	RCTR1(base)	(CAST(VUINT16 *)((base) + 0x09CC)) /* RISC Ctrl Trap 1*/
#define	RCTR2(base)	(CAST(VUINT16 *)((base) + 0x09CE)) /* RISC Ctrl Trap 2*/
#define	RCTR3(base)	(CAST(VUINT16 *)((base) + 0x09D0)) /* RISC Ctrl Trap 3*/
#define	RCTR4(base)	(CAST(VUINT16 *)((base) + 0x09D2)) /* RISC Ctrl Trap 4*/
#define	RTER(base)	(CAST(VUINT16 *)((base) + 0x09D6)) /* RISC Tmr Event*/
#define	RTMR(base)	(CAST(VUINT16 *)((base) + 0x09DA)) /* RISC Tmr Mask */

/* Baud Rate Generation Register set */

#define	BRGC1(base)	(CAST(VUINT32 *)((base) + 0x09F0)) /* BRG1 Config Reg */
#define	BRGC2(base)	(CAST(VUINT32 *)((base) + 0x09F4)) /* BRG2 Config Reg */
#define	BRGC3(base)	(CAST(VUINT32 *)((base) + 0x09F8)) /* BRG3 Config Reg */
#define	BRGC4(base)	(CAST(VUINT32 *)((base) + 0x09FC)) /* BRG4 Config Reg */

/* SCC 1 register set */

#define GSMR_L1(base)	(CAST(VUINT32 *)((base) + 0x0A00)) /* SCC1 Gen Mode*/
#define GSMR_H1(base)	(CAST(VUINT32 *)((base) + 0x0A04)) /* SCC1 Gen Mode*/
#define PSMR1(base)	(CAST(VUINT16 *)((base) + 0x0A08)) /* SCC1 Proto Spec */
#define TODR1(base)	(CAST(VUINT16 *)((base) + 0x0A0C)) /* SCC1 Tx Demand*/
#define DSR1(base)	(CAST(VUINT16 *)((base) + 0x0A0E)) /* SCC1 Data Sync */
#define SCCE1(base)	(CAST(VUINT16 *)((base) + 0x0A10)) /* SCC1 Event Reg */
#define SCCM1(base)	(CAST(VUINT16 *)((base) + 0x0A14)) /* SCC1 Mask Reg */
#define SCCS1(base)	(CAST(VUINT8 *) ((base) + 0x0A17)) /* SCC1 Status Reg */

/* SCC 2 register set */

#define GSMR_L2(base)	(CAST(VUINT32 *)((base) + 0x0A20)) /* SCC2 Gen Mode*/
#define GSMR_H2(base)	(CAST(VUINT32 *)((base) + 0x0A24)) /* SCC2 Gen Mode*/
#define PSMR2(base)	(CAST(VUINT16 *)((base) + 0x0A28)) /* SCC2 Proto Spec */
#define TODR2(base)	(CAST(VUINT16 *)((base) + 0x0A2C)) /* SCC2 Tx Demand*/
#define DSR2(base)	(CAST(VUINT16 *)((base) + 0x0A2E)) /* SCC2 Data Sync */
#define SCCE2(base)	(CAST(VUINT16 *)((base) + 0x0A30)) /* SCC2 Event Reg */
#define SCCM2(base)	(CAST(VUINT16 *)((base) + 0x0A34)) /* SCC2 Mask Reg */
#define SCCS2(base)	(CAST(VUINT8 *)	((base) + 0x0A37)) /* SCC2 Status Reg */

/* SCC 3 register set */

#define GSMR_L3(base)	(CAST(VUINT32 *)((base) + 0x0A40)) /* SCC3 Gen Mode*/
#define GSMR_H3(base)	(CAST(VUINT32 *)((base) + 0x0A44)) /* SCC3 Gen Mode*/