bm8024lib.c

这是motorola公司的powerpc芯片上的嵌入式linux上的驱动程序和测试程序

#include <linux/kernel.h>	/* We're doing kernel work	*/
#include <asm/io.h>

#include "bm8024.h"
#include "bm8024lib.h"
#include "ppc860cpm.h"
#include "ppc860siu.h"

#include "idma.h"


extern char g_dev_mac[6];
/*
* local bm8024 defination
*/
volatile U32   bm8024_virtaddr;


/*init MPC850 memory controler*/
void init_mem_br()
{
	unsigned long immr;
	volatile memctl8xx_t *memctrl_p = 0;	

	asm( "mfspr %0,638": "=r"(immr) : );
	immr &= 0xFFFF0000;
	memctrl_p = (memctl8xx_t *) &((volatile immap_t *)immr)->im_memctl;

	/*init br0 & or0*/
	memctrl_p->memc_br0 = 0x02800801;
	memctrl_p->memc_or0 = 0xFF800940;

	/*init br1 & or1*/
	memctrl_p->memc_or1 = 0xFFFF8124;
	memctrl_p->memc_br1 = 0x80050401;

	/*init br2 & or2*/
	memctrl_p->memc_or2 = 0xFE000800;
	memctrl_p->memc_br2 = 0x00000081;

	/*init br3 & or 3*/
	memctrl_p->memc_or3 = 0xFFFF0984;
	memctrl_p->memc_br3 = 0x80000001;

}
/*
*  BM8024 chipset register function
*/
void bm8024_ioremap()
{
	init_mem_br();
	
	bm8024_virtaddr = (U32) ioremap(BM8024_BASE_ADDR, BM8024_REG_LEN);
	
	return;
}

void bm8024_iounmap()
{
	iounmap((void*)virt_addr);
}

void bm8024_WriteReg(U32 regno,U32 data)
{
	U32 addr = regno + bm8024_virtaddr;
	
	writel(LONGSWAP(data), addr);
}
   
U32 bm8024_ReadReg(U32 regno)
{
	U32 intx;
	U32 addr = regno + bm8024_virtaddr;
	
	intx   = readl(addr);	
	return LONGSWAP(intx);
}

void bm8024_RegBitSet(U32 regno, U32 bit)
{
   U32 data, bitmask;
   
   bitmask = ((U32)1) << bit;
   data = bm8024_ReadReg(regno);
   data |= bitmask; 
   bm8024_WriteReg(regno, data);
   
   return;
}

void bm8024_RegBitClear(U32 regno, U32 bit)
{
   U32 data, bitmask;
   
   bitmask = ((U32)1) << bit;
   data = bm8024_ReadReg(regno);
   data &= (~bitmask); 
   bm8024_WriteReg(regno, data);
   
   return;
}

void bm8024Delay(U32 loop)
{
	U32 i;
	for(i=0; i<loop*10; i++)
	{
		;
	}
}


void bm8024_AddMacToArl(U32 hmac, U32 lmac, U32 portid, U32 flag)
{
   U32   cmd;
   /* Put mac addr[47--16] into AUXR */
   bm8024_WriteReg(0x24, hmac);
   cmd = (lmac << 16) + (pid << 10) + flag;
   bm8024_WriteReg(0x23, cmd);
   
   /*Add a mac address into the address table*/
   bm8024_WriteReg(0x20, 0x109);

}

/*
* bm8024 hard reset
*/
void bm8024_hw_reset()
{

    *PCDIR(immrValue) |= (PORTC_BIT10_HIGH);
    *PCDAT(immrValue) &= (PORTC_BIT10_LOW);  /* pull low for active*/
 
    /* Delay */
    bm8024Delay(100000);
   
    *PCDAT(immrValue) |= (PORTC_BIT10_HIGH); /* pull high for normal*/
    *PCDIR(immrValue) &= (PORTC_BIT10_LOW);
   
    /* Delay */
    bm8024Delay(100000);
}

void	bm8024_SoftReset()
{
   U32 	data0, data1;

   data0 = bm8024_ReadReg(0x07);
   data1 = data0 | 0x40000000;

   bm8024_WriteReg(0x07, data1);
   
   /* Delay  */
    bm8024Delay(100000);

   bm8024_WriteReg(0x07, data0);
}


U32  bm8024_CheckSwitchRsp()
{
   U32	count = 10;
   
   while(count--)
   {
     if (bm8024_ReadReg(0)== ACD_REVISION)
     	return  0;
     
     /* 50ms delay */
      bm8024Delay(100000);
   }
   return -1;
}

void bm8024_chipset_init()
{
    /* initialize IDMA channel */
    IDMA_Init();

    /*HW reset System*/
    bm8024_hw_reset();
    
    /* 55msec delay*/
    bm8024Delay(100000);
	
    data = bm8024_ReadReg(0x01);
    if (data != 0x00000001)
    {
        data = bm8024_ReadReg(6);      
        data |= 0x00100000;      
        bm8024_WriteReg(6, data);   	  
    }
   	
    /* Soft Reset bm8024*/
    bm8024_SoftReset();
   	
    /* 5.5msec delay*/
    bm8024Delay(1000);
	
    /* Check bm8024 response */
    rc = bm8024_CheckSwitchRsp();
    if (rc < 0)
	 return -1;
		
    /* 0.55msec delay*/
    bm8024Delay(100);
 
    bm8024_WriteReg(0xe,0x12ff);	
 
    /* Set the System Configuration Register */
    /*disable dumping all handing*/
    bm8024_WriteReg(6, 0x07F1A00 /*0x047E1a00;*0x47f9a00*/);  /*enable port user-priority*/
    bm8024_WriteReg(0x198, 0x3001); /*set priority of port 25(uplink) to 7*/
 	 	
    /* Set the System Control Register */
    bm8024_WriteReg(7, 0x15f2b00/*0x00054001STANDARD_SWITCH_SETTING*/);
	
    bm8024_WriteReg(0x26, 0x03ffffff);
    bm8024_WriteReg(0x27, 0x03ffffff);
    /*Forwarding unknow DA frame to the dumping port*/
    bm8024_WriteReg(0x25, DUMP_PORT);
    
    /*add cpu MAC*/
    hMac = g_dev_mac[0] << 24 | g_dev_mac[1] << 16 | g_dev_mac[2] << 8 | g_dev_mac[3];
    lMac = g_dev_mac[4] << 8 | g_dev_mac[5];
	
    bm8024_AddMacToArl(hMac, lMac, 26, 0x88); 
    bm8024AddReg89(hMac, lMac);

    /*intrmask --> packet to cpu   or cpu -->bm8024 */
    bm8024_WriteReg(0x11, ISR_BTMSK_TMU_FRAME_DMATO_CPU /*| ISR_BTMSK_RMU_FRAME_RECEIVED*/ );	
   
    /* Disable trunk */
    bm8024_WriteReg(0x1c, 0x00);
	
    /* Enable MIB updating counters */
	
    /*P24/P25*/
    RegBitSet(0x25, 5);
    bm8024Delay(10);
    bm8024_WriteReg(0x20, 0x2ff);
    bm8024Delay(10);
    bm8024_WriteReg(0x20, 0x201);
    bm8024Delay(10);
    /*P0~P24*/
    RegBitClear(0x25, 5);
    bm8024_WriteReg(0x20, 0x2ff);
    bm8024Delay(10);
    bm8024_WriteReg(0x20, 0x201);
	
    /*Enable CPU mode */
    bm8024_WriteReg(0x20, 0x11);    			 
	
}