helloworldbit_mediaengine.c.txt

这是《嵌入式linux－硬件、软件与接口》一书对应的所有linux方面实例的源代码

/*
 * helloworld_bit_mediaengine v1.0 11/03/01
 * www.embeddedlinuxinterfacing.com
 *
 * The original location of this code is
 * http://www.embeddedlinuxinterfacing.com/chapters/09/
 *
 * Copyright (C) 2001 by Craig Hollabaugh
 *
 * This program is free software; you can redistribute it and/or modify 
 * it under the terms of the GNU Library General Public License as 
 * published by the Free Software Foundation; either version 2 of the 
 * License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but 
 * WITHOUT ANY WARRANTY; without even the implied warranty of 
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 
 * Library General Public License for more details.
 *
 * You should have received a copy of the GNU Library General Public 
 * License along with this program; if not, write to the 
 * Free Software Foundation, Inc.,
 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 */

/* helloworld_bit_mediaengine
 * This device driver demonstrates SA1110 I/O and memory controller
 * register configuration. GPIO14 is configured as an output pin 
 * then toggled. CS5 is configured for non burst variable-latency I/O, 
 * 16 bit bus with longest read/write delays at memory address 
 * 0x48000000. After memory controller configuration, accesses to
 * 0x48000000 result in CS5 assertion. Use this device driver and a 
 * fast oscilloscope to capture GPIO14 and memory signals. The
 * SA1110 in the MediaEngine runs at 200MHz, memory access timing is
 * in the nanosecond range.
 */

/* 
arm-linux-gcc -O2 -D__KERNEL__ -DMODULE -I/usr/src/arm-linux/include -c helloworldbit_mediaengine.c  -o /tftpboot/arm-rootfs/tmp/helloworldbit_mediaengine.o
*/

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/proc_fs.h>
#include <asm/uaccess.h>
#include <asm/io.h>

#define MODULE_VERSION "1.0"
#define MODULE_NAME "helloworldbit_mediaengine"

/* see section 9.1.1.1 Intel StrongARM SA-1110 Developer's Manual */
#define GPIO                   0x90040000 /* GPIO registers base address */
#define GPLR_OFFSET            0x00
#define GPDR_OFFSET            0x04
#define GPSR_OFFSET            0x08
#define GPCR_OFFSET            0x0C
#define GAFR_OFFSET            0x1C

#define GPIOLEN                0x20
#define GPIO14                 0x00004000 /* GPIO14 in registers */

#define MEMBASE                0xA0000000 /* mem controller base address */
#define MSC2_OFFSET            0x2C
#define MEMLENGTH              0x30

#define EXPANSIONPORT          0x48000000 /* expansion port base address */
#define EXPANSIONPORTLEN       2

unsigned long int gpdr, gafr, msc2;
static void *io_base, *gpio_base, *mem_base;


/*
 * init_helloworldbit
 *   This function configures the GPDR, GAFR ARM registers for GPIO14 output
 *   Then configures the MCS2 so /CS5 operations are slow as possible
 *   Using a scope or logic probe, load and unload this module to check 
 *   /CS5 and CPIO14 operation
 */
static int __init init_helloworldbit(void)
{
  unsigned char i;

/* get the remapped GPIO controller base address register */
  gpio_base = ioremap_nocache(GPIO, GPIOLEN);
  printk("gpio_base = 0x%08X\n",gpio_base);


/* we need to preserve the other bits in gpdr */
  gpdr = readl(gpio_base + GPDR_OFFSET);
  printk("GPDR      = 0x%08X\n",gpdr);

/* we need to preserve the other bits in gafr */
  gafr = readl(gpio_base + GAFR_OFFSET); 
  printk("GAFR      = 0x%08X\n",gafr);


  writel(gpdr |  GPIO14, gpio_base + GPDR_OFFSET); /* GPIO14 as output */


  writel(gafr & ~GPIO14, gpio_base + GAFR_OFFSET); /* GPIO14 no alt func */

  writel(        GPIO14, gpio_base + GPCR_OFFSET); /* clear GPIO14 */ 
  writel(        GPIO14, gpio_base + GPSR_OFFSET); /* set   GPIO14 */

/* get the remapped memory controller base address register */
  mem_base = ioremap_nocache(MEMBASE, MEMLENGTH);
  printk("mem_base  = 0x%08X\n",mem_base);

/* we need to preserve the other bits in msc2 */
  msc2 = readl(mem_base + MSC2_OFFSET);
  printk("MSC2      = 0x%08X\n",msc2);

/* msc2 is for cs5 and cs4, need to mask off the cs3 part */
/* 0xFFF5, non burst SRAM variable, 16 bits, long delays */
  writel((msc2 & 0x0000FFFF) | 0xFFF50000, mem_base + MSC2_OFFSET);

/* read back the new msc2 value and print it */
  msc2 = readl(mem_base + MSC2_OFFSET);
  printk("MSC2      = 0x%08X\n",msc2);

/* get the remapped expansion port base address */
 io_base = ioremap_nocache(EXPANSIONPORT, EXPANSIONPORTLEN);
  printk("io_base   = 0x%08X\n",io_base);

/* read something from and write a test pattern to the expansion port */
  i = readb(io_base);
  writeb(0xAA,io_base);

/* everything initialized */
  printk(KERN_INFO "%s %s initialized\n",MODULE_NAME, MODULE_VERSION);
  return 0;
}

/*
 * cleanup_helloworldbit
 *   This function restores the GPDR, GAFR, MSC2 registers
 */
static void __exit cleanup_helloworldbit(void)
{
  unsigned char i;

/* toggle /CS5 again for testing */
  i = readb(io_base);
  writeb(0xAA,io_base);

/* toggle GPIO14 again for testing */
  writel(        GPIO14, gpio_base + GPCR_OFFSET); /* clear GPIO14 */ 
  writel(        GPIO14, gpio_base + GPSR_OFFSET); /* set   GPIO14 */

  writel(gpdr, gpio_base + GPDR_OFFSET);  /* restore gpdr */
  writel(gafr, gpio_base + GAFR_OFFSET);  /* restore gafr */
  writel(msc2, mem_base  + MSC2_OFFSET);  /* restore msc2 */

/* release the ioremaps */ 
  iounmap(mem_base); 
  iounmap(gpio_base);
  iounmap(io_base);

  printk(KERN_INFO "%s %s removed\n", MODULE_NAME, MODULE_VERSION);
}

module_init(init_helloworldbit);
module_exit(cleanup_helloworldbit);

MODULE_AUTHOR("Craig Hollabaugh");
MODULE_DESCRIPTION("helloworldbit for MediaEngine");

EXPORT_NO_SYMBOLS;