📄 ledblinker.ic
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sbit CC2_CC26IC_GPX = 0xF174 ^ 8;
sfr CC2_CC27IC = 0xF176;
sbit CC2_CC27IC_IE = 0xF176 ^ 6;
sbit CC2_CC27IC_IR = 0xF176 ^ 7;
sbit CC2_CC27IC_GPX = 0xF176 ^ 8;
sfr CC2_CC28IC = 0xF178;
sbit CC2_CC28IC_IE = 0xF178 ^ 6;
sbit CC2_CC28IC_IR = 0xF178 ^ 7;
sbit CC2_CC28IC_GPX = 0xF178 ^ 8;
sfr CC2_T7IC = 0xF17A;
sbit CC2_T7IC_IE = 0xF17A ^ 6;
sbit CC2_T7IC_IR = 0xF17A ^ 7;
sbit CC2_T7IC_GPX = 0xF17A ^ 8;
sfr CC2_T8IC = 0xF17C;
sbit CC2_T8IC_IE = 0xF17C ^ 6;
sbit CC2_T8IC_IR = 0xF17C ^ 7;
sbit CC2_T8IC_GPX = 0xF17C ^ 8;
sfr EOPIC = 0xF180;
sbit EOPIC_IE = 0xF180 ^ 6;
sbit EOPIC_IR = 0xF180 ^ 7;
sbit EOPIC_GPX = 0xF180 ^ 8;
sfr CC2_CC29IC = 0xF184;
sbit CC2_CC29IC_IE = 0xF184 ^ 6;
sbit CC2_CC29IC_IR = 0xF184 ^ 7;
sbit CC2_CC29IC_GPX = 0xF184 ^ 8;
sfr CC2_CC30IC = 0xF18C;
sbit CC2_CC30IC_IE = 0xF18C ^ 6;
sbit CC2_CC30IC_IR = 0xF18C ^ 7;
sbit CC2_CC30IC_GPX = 0xF18C ^ 8;
sfr CC2_CC31IC = 0xF194;
sbit CC2_CC31IC_IE = 0xF194 ^ 6;
sbit CC2_CC31IC_IR = 0xF194 ^ 7;
sbit CC2_CC31IC_GPX = 0xF194 ^ 8;
sfr CAN_0IC = 0xF196;
sbit CAN_0IC_IE = 0xF196 ^ 6;
sbit CAN_0IC_IR = 0xF196 ^ 7;
sbit CAN_0IC_GPX = 0xF196 ^ 8;
sfr SDLM_IC = 0xF19A;
sbit SDLM_IC_IE = 0xF19A ^ 6;
sbit SDLM_IC_IR = 0xF19A ^ 7;
sbit SDLM_IC_GPX = 0xF19A ^ 8;
sfr ASC0_TBIC = 0xF19C;
sbit ASC0_TBIC_IE = 0xF19C ^ 6;
sbit ASC0_TBIC_IR = 0xF19C ^ 7;
sbit ASC0_TBIC_GPX = 0xF19C ^ 8;
sfr PLLIC = 0xF19E;
sbit PLLIC_PLL = 0xF19E ^ 6;
sbit PLLIC_IR = 0xF19E ^ 7;
sbit PLLIC_GPX = 0xF19E ^ 8;
sfr RTC_IC = 0xF1A0;
sbit RTC_IC_IE = 0xF1A0 ^ 6;
sbit RTC_IC_IR = 0xF1A0 ^ 7;
sbit RTC_IC_GPX = 0xF1A0 ^ 8;
sfr SSC1_TIC = 0xF1AA;
sbit SSC1_TIC_IE = 0xF1AA ^ 6;
sbit SSC1_TIC_IR = 0xF1AA ^ 7;
sbit SSC1_TIC_GPX = 0xF1AA ^ 8;
sfr SSC1_RIC = 0xF1AC;
sbit SSC1_RIC_IE = 0xF1AC ^ 6;
sbit SSC1_RIC_IR = 0xF1AC ^ 7;
sbit SSC1_RIC_GPX = 0xF1AC ^ 8;
sfr SSC1_EIC = 0xF1AE;
sbit SSC1_EIC_IE = 0xF1AE ^ 6;
sbit SSC1_EIC_IR = 0xF1AE ^ 7;
sbit SSC1_EIC_GPX = 0xF1AE ^ 8;
sfr EXICON = 0xF1C0;
sfr GPT12E_T2IC = 0xFF60;
sbit GPT12E_T2IC_IE = 0xFF60 ^ 6;
sbit GPT12E_T2IC_IR = 0xFF60 ^ 7;
sbit GPT12E_T2IC_GPX = 0xFF60 ^ 8;
sfr GPT12E_T3IC = 0xFF62;
sbit GPT12E_T3IC_IE = 0xFF62 ^ 6;
sbit GPT12E_T3IC_IR = 0xFF62 ^ 7;
sbit GPT12E_T3IC_GPX = 0xFF62 ^ 8;
sfr GPT12E_T4IC = 0xFF64;
sbit GPT12E_T4IC_IE = 0xFF64 ^ 6;
sbit GPT12E_T4IC_IR = 0xFF64 ^ 7;
sbit GPT12E_T4IC_GPX = 0xFF64 ^ 8;
sfr GPT12E_T5IC = 0xFF66;
sbit GPT12E_T5IC_IE = 0xFF66 ^ 6;
sbit GPT12E_T5IC_IR = 0xFF66 ^ 7;
sbit GPT12E_T5IC_GPX = 0xFF66 ^ 8;
sfr GPT12E_T6IC = 0xFF68;
sbit GPT12E_T6IC_IE = 0xFF68 ^ 6;
sbit GPT12E_T6IC_IR = 0xFF68 ^ 7;
sbit GPT12E_T6IC_GPX = 0xFF68 ^ 8;
sfr GPT12E_CRIC = 0xFF6A;
sbit GPT12E_CRIC_IE = 0xFF6A ^ 6;
sbit GPT12E_CRIC_IR = 0xFF6A ^ 7;
sbit GPT12E_CRIC_GPX = 0xFF6A ^ 8;
sfr ASC0_TIC = 0xFF6C;
sbit ASC0_TIC_IE = 0xFF6C ^ 6;
sbit ASC0_TIC_IR = 0xFF6C ^ 7;
sbit ASC0_TIC_GPX = 0xFF6C ^ 8;
sfr ASC0_RIC = 0xFF6E;
sbit ASC0_RIC_IE = 0xFF6E ^ 6;
sbit ASC0_RIC_IR = 0xFF6E ^ 7;
sbit ASC0_RIC_GPX = 0xFF6E ^ 8;
sfr ASC0_EIC = 0xFF70;
sbit ASC0_EIC_IE = 0xFF70 ^ 6;
sbit ASC0_EIC_IR = 0xFF70 ^ 7;
sbit ASC0_EIC_GPX = 0xFF70 ^ 8;
sfr SSC0_TIC = 0xFF72;
sbit SSC0_TIC_IE = 0xFF72 ^ 6;
sbit SSC0_TIC_IR = 0xFF72 ^ 7;
sbit SSC0_TIC_GPX = 0xFF72 ^ 8;
sfr SSC0_RIC = 0xFF74;
sbit SSC0_RIC_IE = 0xFF74 ^ 6;
sbit SSC0_RIC_IR = 0xFF74 ^ 7;
sbit SSC0_RIC_GPX = 0xFF74 ^ 8;
sfr SSC0_EIC = 0xFF76;
sbit SSC0_EIC_IE = 0xFF76 ^ 6;
sbit SSC0_EIC_IR = 0xFF76 ^ 7;
sbit SSC0_EIC_GPX = 0xFF76 ^ 8;
sfr CC1_CC0IC = 0xFF78;
sbit CC1_CC0IC_IE = 0xFF78 ^ 6;
sbit CC1_CC0IC_IR = 0xFF78 ^ 7;
sbit CC1_CC0IC_GPX = 0xFF78 ^ 8;
sfr CC1_CC1IC = 0xFF7A;
sbit CC1_CC1IC_IE = 0xFF7A ^ 6;
sbit CC1_CC1IC_IR = 0xFF7A ^ 7;
sbit CC1_CC1IC_GPX = 0xFF7A ^ 8;
sfr CC1_CC2IC = 0xFF7C;
sbit CC1_CC2IC_IE = 0xFF7C ^ 6;
sbit CC1_CC2IC_IR = 0xFF7C ^ 7;
sbit CC1_CC2IC_GPX = 0xFF7C ^ 8;
sfr CC1_CC3IC = 0xFF7E;
sbit CC1_CC3IC_IE = 0xFF7E ^ 6;
sbit CC1_CC3IC_IR = 0xFF7E ^ 7;
sbit CC1_CC3IC_GPX = 0xFF7E ^ 8;
sfr CC1_CC4IC = 0xFF80;
sbit CC1_CC4IC_IE = 0xFF80 ^ 6;
sbit CC1_CC4IC_IR = 0xFF80 ^ 7;
sbit CC1_CC4IC_GPX = 0xFF80 ^ 8;
sfr CC1_CC5IC = 0xFF82;
sbit CC1_CC5IC_IE = 0xFF82 ^ 6;
sbit CC1_CC5IC_IR = 0xFF82 ^ 7;
sbit CC1_CC5IC_GPX = 0xFF82 ^ 8;
sfr CC1_CC6IC = 0xFF84;
sbit CC1_CC6IC_IE = 0xFF84 ^ 6;
sbit CC1_CC6IC_IR = 0xFF84 ^ 7;
sbit CC1_CC6IC_GPX = 0xFF84 ^ 8;
sfr CC1_CC7IC = 0xFF86;
sbit CC1_CC7IC_IE = 0xFF86 ^ 6;
sbit CC1_CC7IC_IR = 0xFF86 ^ 7;
sbit CC1_CC7IC_GPX = 0xFF86 ^ 8;
sfr CC1_CC8IC = 0xFF88;
sbit CC1_CC8IC_IE = 0xFF88 ^ 6;
sbit CC1_CC8IC_IR = 0xFF88 ^ 7;
sbit CC1_CC8IC_GPX = 0xFF88 ^ 8;
sfr CC1_CC9IC = 0xFF8A;
sbit CC1_CC9IC_IE = 0xFF8A ^ 6;
sbit CC1_CC9IC_IR = 0xFF8A ^ 7;
sbit CC1_CC9IC_GPX = 0xFF8A ^ 8;
sfr CC1_CC10IC = 0xFF8C;
sbit CC1_CC10IC_IE = 0xFF8C ^ 6;
sbit CC1_CC10IC_IR = 0xFF8C ^ 7;
sbit CC1_CC10IC_GPX = 0xFF8C ^ 8;
sfr CC1_CC11IC = 0xFF8E;
sbit CC1_CC11IC_IE = 0xFF8E ^ 6;
sbit CC1_CC11IC_IR = 0xFF8E ^ 7;
sbit CC1_CC11IC_GPX = 0xFF8E ^ 8;
sfr CC1_CC12IC = 0xFF90;
sbit CC1_CC12IC_IE = 0xFF90 ^ 6;
sbit CC1_CC12IC_IR = 0xFF90 ^ 7;
sbit CC1_CC12IC_GPX = 0xFF90 ^ 8;
sfr CC1_CC13IC = 0xFF92;
sbit CC1_CC13IC_IE = 0xFF92 ^ 6;
sbit CC1_CC13IC_IR = 0xFF92 ^ 7;
sbit CC1_CC13IC_GPX = 0xFF92 ^ 8;
sfr CC1_CC14IC = 0xFF94;
sbit CC1_CC14IC_IE = 0xFF94 ^ 6;
sbit CC1_CC14IC_IR = 0xFF94 ^ 7;
sbit CC1_CC14IC_GPX = 0xFF94 ^ 8;
sfr CC1_CC15IC = 0xFF96;
sbit CC1_CC15IC_IE = 0xFF96 ^ 6;
sbit CC1_CC15IC_IR = 0xFF96 ^ 7;
sbit CC1_CC15IC_GPX = 0xFF96 ^ 8;
sfr ADC_CIC = 0xFF98;
sbit ADC_CIC_IE = 0xFF98 ^ 6;
sbit ADC_CIC_IR = 0xFF98 ^ 7;
sbit ADC_CIC_GPX = 0xFF98 ^ 8;
sfr ADC_EIC = 0xFF9A;
sbit ADC_EIC_IE = 0xFF9A ^ 6;
sbit ADC_EIC_IR = 0xFF9A ^ 7;
sbit ADC_EIC_GPX = 0xFF9A ^ 8;
sfr CC1_T0IC = 0xFF9C;
sbit CC1_T0IC_IE = 0xFF9C ^ 6;
sbit CC1_T0IC_IR = 0xFF9C ^ 7;
sbit CC1_T0IC_GPX = 0xFF9C ^ 8;
sfr CC1_T1IC = 0xFF9E;
sbit CC1_T1IC_IE = 0xFF9E ^ 6;
sbit CC1_T1IC_IR = 0xFF9E ^ 7;
sbit CC1_T1IC_GPX = 0xFF9E ^ 8;
sfr TFR = 0xFFAC;
sbit TFR_ILLOPA = 0xFFAC ^ 2;
sbit TFR_PRTFLT = 0xFFAC ^ 3;
sbit TFR_PACER = 0xFFAC ^ 4;
sbit TFR_UNDOPC = 0xFFAC ^ 7;
sbit TFR_SOFTBRK = 0xFFAC ^ 12;
sbit TFR_STKUF = 0xFFAC ^ 13;
sbit TFR_STKOF = 0xFFAC ^ 14;
sbit TFR_NMI = 0xFFAC ^ 15;
sfr QX0 = 0xF000;
sfr QX1 = 0xF002;
sfr QR0 = 0xF004;
sfr QR1 = 0xF006;
sfr PECC0 = 0xFEC0;
sfr PECC1 = 0xFEC2;
sfr PECC2 = 0xFEC4;
sfr PECC3 = 0xFEC6;
sfr PECC4 = 0xFEC8;
sfr PECC5 = 0xFECA;
sfr PECC6 = 0xFECC;
sfr PECC7 = 0xFECE;
sfr PECISNC = 0xFFA8;
sbit PECISNC_C0IE = 0xFFA8 ^ 0;
sbit PECISNC_C0IR = 0xFFA8 ^ 1;
sbit PECISNC_C1IE = 0xFFA8 ^ 2;
sbit PECISNC_C1IR = 0xFFA8 ^ 3;
sbit PECISNC_C2IE = 0xFFA8 ^ 4;
sbit PECISNC_C2IR = 0xFFA8 ^ 5;
sbit PECISNC_C3IE = 0xFFA8 ^ 6;
sbit PECISNC_C3IR = 0xFFA8 ^ 7;
sbit PECISNC_C4IE = 0xFFA8 ^ 8;
sbit PECISNC_C4IR = 0xFFA8 ^ 9;
sbit PECISNC_C5IE = 0xFFA8 ^ 10;
sbit PECISNC_C5IR = 0xFFA8 ^ 11;
sbit PECISNC_C6IE = 0xFFA8 ^ 12;
sbit PECISNC_C6IR = 0xFFA8 ^ 13;
sbit PECISNC_C7IE = 0xFFA8 ^ 14;
sbit PECISNC_C7IR = 0xFFA8 ^ 15;
sfr POCON0L = 0xF080;
sfr POCON0H = 0xF082;
sfr POCON1L = 0xF084;
sfr POCON1H = 0xF086;
sfr POCON3 = 0xF08A;
sfr POCON4 = 0xF08C;
sfr POCON9 = 0xF094;
sfr POCON20 = 0xF0AA;
sfr DP0L = 0xF100;
sbit DP0L_P0 = 0xF100 ^ 0;
sbit DP0L_P1 = 0xF100 ^ 1;
sbit DP0L_P2 = 0xF100 ^ 2;
sbit DP0L_P3 = 0xF100 ^ 3;
sbit DP0L_P4 = 0xF100 ^ 4;
sbit DP0L_P5 = 0xF100 ^ 5;
sbit DP0L_P6 = 0xF100 ^ 6;
sbit DP0L_P7 = 0xF100 ^ 7;
sfr DP0H = 0xF102;
sbit DP0H_P0 = 0xF102 ^ 0;
sbit DP0H_P1 = 0xF102 ^ 1;
sbit DP0H_P2 = 0xF102 ^ 2;
sbit DP0H_P3 = 0xF102 ^ 3;
sbit DP0H_P4 = 0xF102 ^ 4;
sbit DP0H_P5 = 0xF102 ^ 5;
sbit DP0H_P6 = 0xF102 ^ 6;
sbit DP0H_P7 = 0xF102 ^ 7;
sfr DP1L = 0xF104;
sbit DP1L_P0 = 0xF104 ^ 0;
sbit DP1L_P1 = 0xF104 ^ 1;
sbit DP1L_P2 = 0xF104 ^ 2;
sbit DP1L_P3 = 0xF104 ^ 3;
sbit DP1L_P4 = 0xF104 ^ 4;
sbit DP1L_P5 = 0xF104 ^ 5;
sbit DP1L_P6 = 0xF104 ^ 6;
sbit DP1L_P7 = 0xF104 ^ 7;
sfr DP1H = 0xF106;
sbit DP1H_P0 = 0xF106 ^ 0;
sbit DP1H_P1 = 0xF106 ^ 1;
sbit DP1H_P2 = 0xF106 ^ 2;
sbit DP1H_P3 = 0xF106 ^ 3;
sbit DP1H_P4 = 0xF106 ^ 4;
sbit DP1H_P5 = 0xF106 ^ 5;
sbit DP1H_P6 = 0xF106 ^ 6;
sbit DP1H_P7 = 0xF106 ^ 7;
sfr ALTSEL0P1H = 0xF120;
sbit ALTSEL0P1H_P0 = 0xF120 ^ 0;
sbit ALTSEL0P1H_P1 = 0xF120 ^ 1;
sbit ALTSEL0P1H_P2 = 0xF120 ^ 2;
sbit ALTSEL0P1H_P3 = 0xF120 ^ 3;
sbit ALTSEL0P1H_P4 = 0xF120 ^ 4;
sbit ALTSEL0P1H_P5 = 0xF120 ^ 5;
sbit ALTSEL0P1H_P6 = 0xF120 ^ 6;
sbit ALTSEL0P1H_P7 = 0xF120 ^ 7;
sfr ALTSEL0P3 = 0xF126;
sbit ALTSEL0P3_P1 = 0xF126 ^ 1;
sbit ALTSEL0P3_P3 = 0xF126 ^ 3;
sbit ALTSEL0P3_P8 = 0xF126 ^ 8;
sbit ALTSEL0P3_P9 = 0xF126 ^ 9;
sbit ALTSEL0P3_P10 = 0xF126 ^ 10;
sbit ALTSEL0P3_P11 = 0xF126 ^ 11;
sbit ALTSEL0P3_P13 = 0xF126 ^ 13;
sfr ALTSEL1P3 = 0xF128;
sbit ALTSEL1P3_P1 = 0xF128 ^ 1;
sfr ALTSEL0P4 = 0xF12A;
sbit ALTSEL0P4_P6 = 0xF12A ^ 6;
sbit ALTSEL0P4_P7 = 0xF12A ^ 7;
sfr ALTSEL0P1L = 0xF130;
sbit ALTSEL0P1L_P0 = 0xF130 ^ 0;
sbit ALTSEL0P1L_P1 = 0xF130 ^ 1;
sbit ALTSEL0P1L_P2 = 0xF130 ^ 2;
sbit ALTSEL0P1L_P3 = 0xF130 ^ 3;
sbit ALTSEL0P1L_P4 = 0xF130 ^ 4;
sbit ALTSEL0P1L_P5 = 0xF130 ^ 5;
sbit ALTSEL0P1L_P6 = 0xF130 ^ 6;
sbit ALTSEL0P1L_P7 = 0xF130 ^ 7;
sfr ALTSEL1P4 = 0xF136;
sbit ALTSEL1P4_P7 = 0xF136 ^ 7;
sfr ALTSEL0P9 = 0xF138;
sbit ALTSEL0P9_P0 = 0xF138 ^ 0;
sbit ALTSEL0P9_P1 = 0xF138 ^ 1;
sbit ALTSEL0P9_P2 = 0xF138 ^ 2;
sbit ALTSEL0P9_P3 = 0xF138 ^ 3;
sbit ALTSEL0P9_P4 = 0xF138 ^ 4;
sbit ALTSEL0P9_P5 = 0xF138 ^ 5;
sfr ALTSEL1P9 = 0xF13A;
sbit ALTSEL1P9_P0 = 0xF13A ^ 0;
sbit ALTSEL1P9_P1 = 0xF13A ^ 1;
sbit ALTSEL1P9_P2 = 0xF13A ^ 2;
sbit ALTSEL1P9_P3 = 0xF13A ^ 3;
sbit ALTSEL1P9_P4 = 0xF13A ^ 4;
sbit ALTSEL1P9_P5 = 0xF13A ^ 5;
sfr PICON = 0xF1C4;
sbit PICON_P3LIN = 0xF1C4 ^ 2;
sbit PICON_P3HIN = 0xF1C4 ^ 3;
sbit PICON_P4LIN = 0xF1C4 ^ 4;
sbit PICON_P9LIN = 0xF1C4 ^ 7;
sbit PICON_P20LIN = 0xF1C4 ^ 8;
sbit PICON_P20HIN = 0xF1C4 ^ 9;
sfr ODP3 = 0xF1C6;
sbit ODP3_P0 = 0xF1C6 ^ 0;
sbit ODP3_P1 = 0xF1C6 ^ 1;
sbit ODP3_P2 = 0xF1C6 ^ 2;
sbit ODP3_P3 = 0xF1C6 ^ 3;
sbit ODP3_P4 = 0xF1C6 ^ 4;
sbit ODP3_P5 = 0xF1C6 ^ 5;
sbit ODP3_P6 = 0xF1C6 ^ 6;
sbit ODP3_P7 = 0xF1C6 ^ 7;
sbit ODP3_P8 = 0xF1C6 ^ 8;
sbit ODP3_P9 = 0xF1C6 ^ 9;
sbit ODP3_P10 = 0xF1C6 ^ 10;
sbit ODP3_P11 = 0xF1C6 ^ 11;
sbit ODP3_P13 = 0xF1C6 ^ 13;
sfr ODP4 = 0xF1CA;
sbit ODP4_P0 = 0xF1CA ^ 0;
sbit ODP4_P1 = 0xF1CA ^ 1;
sbit ODP4_P2 = 0xF1CA ^ 2;
sbit ODP4_P3 = 0xF1CA ^ 3;
sbit ODP4_P4 = 0xF1CA ^ 4;
sbit ODP4_P5 = 0xF1CA ^ 5;
sbit ODP4_P6 = 0xF1CA ^ 6;
sbit ODP4_P7 = 0xF1CA ^ 7;
sfr P0L = 0xFF00;
sbit P0L_P0 = 0xFF00 ^ 0;
sbit P0L_P1 = 0xFF00 ^ 1;
sbit P0L_P2 = 0xFF00 ^ 2;
sbit P0L_P3 = 0xFF00 ^ 3;
sbit P0L_P4 = 0xFF00 ^ 4;
sbit P0L_P5 = 0xFF00 ^ 5;
sbit P0L_P6 = 0xFF00 ^ 6;
sbit P0L_P7 = 0xFF00 ^ 7;
sfr P0H = 0xFF02;
sbit P0H_P0 = 0xFF02 ^ 0;
sbit P0H_P1 = 0xFF02 ^ 1;
sbit P0H_P2 = 0xFF02 ^ 2;
sbit P0H_P3 = 0xFF02 ^ 3;
sbit P0H_P4 = 0xFF02 ^ 4;
sbit P0H_P5 = 0xFF02 ^ 5;
sbit P0H_P6 = 0xFF02 ^ 6;
sbit P0H_P7 = 0xFF02 ^ 7;
sfr P1L = 0xFF04;
sbit P1L_P0 = 0xFF04 ^ 0;
sbit P1L_P1 = 0xFF04 ^ 1;
sbit P1L_P2 = 0xFF04 ^ 2;
sbit P1L_P3 = 0xFF04 ^ 3;
sbit P1L_P4 = 0xFF04 ^ 4;
sbit P1L_P5 = 0xFF04 ^ 5;
sbit P1L_P6 = 0xFF04 ^ 6;
sbit P1L_P7 = 0xFF04 ^ 7;
sfr P1H = 0xFF06;
sbit P1H_P0 = 0xFF06 ^ 0;
sbit P1H_P1 = 0xFF06 ^ 1;
sbit P1H_P2 = 0xFF06 ^ 2;
sbit P1H_P3 = 0xFF06 ^ 3;
sbit P1H_P4 = 0xFF06 ^ 4;
sbit P1H_P5 = 0xFF06 ^ 5;
sbit P1H_P6 = 0xFF06 ^ 6;
sbit P1H_P7 = 0xFF06 ^ 7;
sfr P9 = 0xFF16;
sbit P9_P0 = 0xFF16 ^ 0;
sbit P9_P1 = 0xFF16 ^ 1;
sbit P9_P2 = 0xFF16 ^ 2;
sbit P9_P3 = 0xFF16 ^ 3;
sbit P9_P4 = 0xFF16 ^ 4;
sbit P9_P5 = 0xFF16 ^ 5;
sfr DP9 = 0xFF18;
sbit DP9_P0 = 0xFF18 ^ 0;
sbit DP9_P1 = 0xFF18 ^ 1;
sbit DP9_P2 = 0xFF18 ^ 2;
sbit DP9_P3 = 0xFF18 ^ 3;
sbit DP9_P4 = 0xFF18 ^ 4;
sbit DP9_P5 = 0xFF18 ^ 5;
sfr ODP9 = 0xFF1A;
sbit ODP9_P0 = 0xFF1A ^ 0;
sbit ODP9_P1 = 0xFF1A ^ 1;
sbit ODP9_P2 = 0xFF1A ^ 2;
sbit ODP9_P3 = 0xFF1A ^ 3;
sbit ODP9_P4 = 0xFF1A ^ 4;
sbit ODP9_P5 = 0xFF1A ^ 5;
sfr P5 = 0xFFA2;
sbit P5_P0 = 0xFFA2 ^ 0;
sbit P5_P1 = 0xFFA2 ^ 1;
sbit P5_P2 = 0xFFA2 ^ 2;
sbit P5_P3 = 0xFFA2 ^ 3;
sbit P5_P4 = 0xFFA2 ^ 4;
sbit P5_P5 = 0xFFA2 ^ 5;
sbit P5_P6 = 0xFFA2 ^ 6;
sbit P5_P7 = 0xFFA2 ^ 7;
sbit P5_P10 = 0xFFA2 ^ 10;
sbit P5_P11 = 0xFFA2 ^ 11;
sbit P5_P12 = 0xFFA2 ^ 12;
sbit P5_P13 = 0xFFA2 ^ 13;
sbit P5_P14 = 0xFFA2 ^ 14;
sbit P5_P15 = 0xFFA2 ^ 15;
sfr P5DIDIS = 0xFFA4;
sbit P5DIDIS_P0 = 0xFFA4 ^ 0;
sbit P5DIDIS_P1 = 0xFFA4 ^ 1;
sbit P5DIDIS_P2 = 0xFFA4 ^ 2;
sbit P5DIDIS_P3 = 0xFFA4 ^ 3;
sbit P5DIDIS_P4 = 0xFFA4 ^ 4;
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