ledblinker.ic

这个文件是西门子16位单片机从c166上的一些应用程序的源代码

// v_2.45.2, Wed Sep 15 12:30:51 2004
#line 1 "src\\LEDBlinker.cpp"
#line 3 "inc\\LEDBlinker.h"
struct LEDBlinker; extern void *__nw__FUi(unsigned); extern void __dl__FPv(void *);
#line 32 "C:\\Keil\\C166\\INC\\stdio.h"
extern int printf(const char *, ...);
#line 39 "src\\LEDBlinker.cpp"
extern void Initialise__10LEDBlinkerFv(struct LEDBlinker *const);
#line 51
extern void RunLights__10LEDBlinkerFv(struct LEDBlinker *const);
#line 13
extern struct LEDBlinker *GetInst__10LEDBlinkerSFv(void);
#line 30
extern void DeleteInstance__10LEDBlinkerSFv(void);
#line 21
extern struct LEDBlinker *__ct__10LEDBlinkerFv(struct LEDBlinker *);




extern void __dt__10LEDBlinkerFv(struct LEDBlinker *const, int);
#line 44
extern void Delay__10LEDBlinkerFv(struct LEDBlinker *const);
#line 10
extern struct LEDBlinker *m_pInstance__10LEDBlinker;
#line 14 "C:\\Keil\\C166\\INC\\XC16x.H"
 sfr ADC_CTR2 = 0xF09C;
 sfr ADC_CTR2IN = 0xF09E;
 sfr ADC_DAT2 = 0xF0A0;
 sfr ADC_DAT = 0xFEA0;
 sfr ADC_ID = 0xFEA8;
 sfr ADC_CON = 0xFFA0;
sbit ADC_CON_ADST = 0xFFA0 ^ 7;
sbit ADC_CON_ADBSY = 0xFFA0 ^ 8;
sbit ADC_CON_ADWR = 0xFFA0 ^ 9;
sbit ADC_CON_ADCIN = 0xFFA0 ^ 10;
sbit ADC_CON_ADCRQ = 0xFFA0 ^ 11;
 sfr ADC_CON1 = 0xFFA6;
sbit ADC_CON1_RES = 0xFFA6 ^ 12;
sbit ADC_CON1_CAL = 0xFFA6 ^ 13;
sbit ADC_CON1_SAMPLE = 0xFFA6 ^ 14;
sbit ADC_CON1_ICST = 0xFFA6 ^ 15;
 sfr ADC_CTR0 = 0xFFBE;
sbit ADC_CTR0_ADST = 0xFFBE ^ 7;
sbit ADC_CTR0_ADBSY = 0xFFBE ^ 8;
sbit ADC_CTR0_ADWR = 0xFFBE ^ 9;
sbit ADC_CTR0_ADCIN = 0xFFBE ^ 10;
sbit ADC_CTR0_ADCRQ = 0xFFBE ^ 11;
sbit ADC_CTR0_SAMPLE = 0xFFBE ^ 14;
sbit ADC_CTR0_MD = 0xFFBE ^ 15;


 sfr ASC0_ABSTAT = 0xF0B8;
 sfr ASC0_FSTAT = 0xF0BA;
 sfr ASC0_TXFCON = 0xF0C4;
 sfr ASC0_RXFCON = 0xF0C6;
 sfr ASC0_ABCON = 0xF1B8;
sbit ASC0_ABCON_ABEN = 0xF1B8 ^ 0;
sbit ASC0_ABCON_AUREN = 0xF1B8 ^ 1;
sbit ASC0_ABCON_ABSTEN = 0xF1B8 ^ 2;
sbit ASC0_ABCON_ABDETEN = 0xF1B8 ^ 3;
sbit ASC0_ABCON_FCDETEN = 0xF1B8 ^ 4;
sbit ASC0_ABCON_TXINV = 0xF1B8 ^ 10;
sbit ASC0_ABCON_RXINV = 0xF1B8 ^ 11;
 sfr ASC0_PMW = 0xFEAA;
 sfr ASC0_TBUF = 0xFEB0;
 sfr ASC0_RBUF = 0xFEB2;
 sfr ASC0_BG = 0xFEB4;
 sfr ASC0_FDV = 0xFEB6;
 sfr ASC0_CON = 0xFFB0;
sbit ASC0_CON_STP = 0xFFB0 ^ 3;
sbit ASC0_CON_REN = 0xFFB0 ^ 4;
sbit ASC0_CON_PEN_RXDI = 0xFFB0 ^ 5;
sbit ASC0_CON_FEN = 0xFFB0 ^ 6;
sbit ASC0_CON_OEN = 0xFFB0 ^ 7;
sbit ASC0_CON_PE = 0xFFB0 ^ 8;
sbit ASC0_CON_FE = 0xFFB0 ^ 9;
sbit ASC0_CON_OE = 0xFFB0 ^ 10;
sbit ASC0_CON_S0FDE = 0xFFB0 ^ 11;
sbit ASC0_CON_ODD = 0xFFB0 ^ 12;
sbit ASC0_CON_BRS = 0xFFB0 ^ 13;
sbit ASC0_CON_LB = 0xFFB0 ^ 14;
sbit ASC0_CON_R = 0xFFB0 ^ 15;



 sfr ASC1_TXFCON = 0xF0A4;
 sfr ASC1_RXFCON = 0xF0A6;
 sfr ASC1_ABSTAT = 0xF0BC;
 sfr ASC1_FSTAT = 0xF0BE;
 sfr ASC1_ABCON = 0xF1BC;
sbit ASC1_ABCON_ABEN = 0xF1BC ^ 0;
sbit ASC1_ABCON_AUREN = 0xF1BC ^ 1;
sbit ASC1_ABCON_ABSTEN = 0xF1BC ^ 2;
sbit ASC1_ABCON_ABDETEN = 0xF1BC ^ 3;
sbit ASC1_ABCON_FCDETEN = 0xF1BC ^ 4;
sbit ASC1_ABCON_TXINV = 0xF1BC ^ 10;
sbit ASC1_ABCON_RXINV = 0xF1BC ^ 11;
 sfr ASC1_PMW = 0xFEAC;
 sfr ASC1_TBUF = 0xFEB8;
 sfr ASC1_RBUF = 0xFEBA;
 sfr ASC1_BG = 0xFEBC;
 sfr ASC1_FDV = 0xFEBE;
 sfr ASC1_CON = 0xFFB8;
sbit ASC1_CON_STP = 0xFFB8 ^ 3;
sbit ASC1_CON_REN = 0xFFB8 ^ 4;
sbit ASC1_CON_PEN = 0xFFB8 ^ 5;
sbit ASC1_CON_FEN = 0xFFB8 ^ 6;
sbit ASC1_CON_OEN = 0xFFB8 ^ 7;
sbit ASC1_CON_PE = 0xFFB8 ^ 8;
sbit ASC1_CON_FE = 0xFFB8 ^ 9;
sbit ASC1_CON_OE = 0xFFB8 ^ 10;
sbit ASC1_CON_S0FDE = 0xFFB8 ^ 11;
sbit ASC1_CON_ODD = 0xFFB8 ^ 12;
sbit ASC1_CON_BRS = 0xFFB8 ^ 13;
sbit ASC1_CON_LB = 0xFFB8 ^ 14;
sbit ASC1_CON_R = 0xFFB8 ^ 15;



 sfr CC1_IOC = 0xF062;
 sfr CC1_SEM = 0xFE2C;
 sfr CC1_SEE = 0xFE2E;
 sfr CC1_T0 = 0xFE50;
 sfr CC1_T1 = 0xFE52;
 sfr CC1_T0REL = 0xFE54;
 sfr CC1_T1REL = 0xFE56;
 sfr CC1_CC0 = 0xFE80;
 sfr CC1_CC1 = 0xFE82;
 sfr CC1_CC2 = 0xFE84;
 sfr CC1_CC3 = 0xFE86;
 sfr CC1_CC4 = 0xFE88;
 sfr CC1_CC5 = 0xFE8A;
 sfr CC1_CC6 = 0xFE8C;
 sfr CC1_CC7 = 0xFE8E;
 sfr CC1_CC8 = 0xFE90;
 sfr CC1_CC9 = 0xFE92;
 sfr CC1_CC10 = 0xFE94;
 sfr CC1_CC11 = 0xFE96;
 sfr CC1_CC12 = 0xFE98;
 sfr CC1_CC13 = 0xFE9A;
 sfr CC1_CC14 = 0xFE9C;
 sfr CC1_CC15 = 0xFE9E;
 sfr CC1_T01CON = 0xFF50;
sbit CC1_T01CON_T0M = 0xFF50 ^ 3;
sbit CC1_T01CON_T0R = 0xFF50 ^ 6;
sbit CC1_T01CON_T1M = 0xFF50 ^ 11;
sbit CC1_T01CON_T1R = 0xFF50 ^ 14;
 sfr CC1_M0 = 0xFF52;
sbit CC1_M0_ACC0 = 0xFF52 ^ 3;
sbit CC1_M0_ACC1 = 0xFF52 ^ 7;
sbit CC1_M0_ACC2 = 0xFF52 ^ 11;
sbit CC1_M0_ACC3 = 0xFF52 ^ 15;
 sfr CC1_M1 = 0xFF54;
sbit CC1_M1_ACC4 = 0xFF54 ^ 3;
sbit CC1_M1_ACC5 = 0xFF54 ^ 7;
sbit CC1_M1_ACC6 = 0xFF54 ^ 11;
sbit CC1_M1_ACC7 = 0xFF54 ^ 15;
 sfr CC1_M2 = 0xFF56;
sbit CC1_M2_ACC8 = 0xFF56 ^ 3;
sbit CC1_M2_ACC9 = 0xFF56 ^ 7;
sbit CC1_M2_ACC10 = 0xFF56 ^ 11;
sbit CC1_M2_ACC11 = 0xFF56 ^ 15;
 sfr CC1_M3 = 0xFF58;
sbit CC1_M3_ACC12 = 0xFF58 ^ 3;
sbit CC1_M3_ACC13 = 0xFF58 ^ 7;
sbit CC1_M3_ACC14 = 0xFF58 ^ 11;
sbit CC1_M3_ACC15 = 0xFF58 ^ 15;
 sfr CC1_DRM = 0xFF5A;
 sfr CC1_OUT = 0xFF5C;
sbit CC1_OUT_CC0IO = 0xFF5C ^ 0;
sbit CC1_OUT_CC1IO = 0xFF5C ^ 1;
sbit CC1_OUT_CC2IO = 0xFF5C ^ 2;
sbit CC1_OUT_CC3IO = 0xFF5C ^ 3;
sbit CC1_OUT_CC4IO = 0xFF5C ^ 4;
sbit CC1_OUT_CC5IO = 0xFF5C ^ 5;
sbit CC1_OUT_CC6IO = 0xFF5C ^ 6;
sbit CC1_OUT_CC7IO = 0xFF5C ^ 7;
sbit CC1_OUT_CC8IO = 0xFF5C ^ 8;
sbit CC1_OUT_CC9IO = 0xFF5C ^ 9;
sbit CC1_OUT_CC10IO = 0xFF5C ^ 10;
sbit CC1_OUT_CC11IO = 0xFF5C ^ 11;
sbit CC1_OUT_CC12IO = 0xFF5C ^ 12;
sbit CC1_OUT_CC13IO = 0xFF5C ^ 13;
sbit CC1_OUT_CC14IO = 0xFF5C ^ 14;
sbit CC1_OUT_CC15IO = 0xFF5C ^ 15;




 sfr CC2_T7 = 0xF050;
 sfr CC2_T8 = 0xF052;
 sfr CC2_T7REL = 0xF054;
 sfr CC2_T8REL = 0xF056;
 sfr CC2_IOC = 0xF066;
 sfr CC2_SEM = 0xFE28;
 sfr CC2_SEE = 0xFE2A;
 sfr CC2_CC16 = 0xFE60;
 sfr CC2_CC17 = 0xFE62;
 sfr CC2_CC18 = 0xFE64;
 sfr CC2_CC19 = 0xFE66;
 sfr CC2_CC20 = 0xFE68;
 sfr CC2_CC21 = 0xFE6A;
 sfr CC2_CC22 = 0xFE6C;
 sfr CC2_CC23 = 0xFE6E;
 sfr CC2_CC24 = 0xFE70;
 sfr CC2_CC25 = 0xFE72;
 sfr CC2_CC26 = 0xFE74;
 sfr CC2_CC27 = 0xFE76;
 sfr CC2_CC28 = 0xFE78;
 sfr CC2_CC29 = 0xFE7A;
 sfr CC2_CC30 = 0xFE7C;
 sfr CC2_CC31 = 0xFE7E;
 sfr CC2_T78CON = 0xFF20;
sbit CC2_T78CON_T7M = 0xFF20 ^ 3;
sbit CC2_T78CON_T7R = 0xFF20 ^ 6;
sbit CC2_T78CON_T8M = 0xFF20 ^ 11;
sbit CC2_T78CON_T8R = 0xFF20 ^ 14;
 sfr CC2_M4 = 0xFF22;
sbit CC2_M4_ACC16 = 0xFF22 ^ 3;
sbit CC2_M4_ACC17 = 0xFF22 ^ 7;
sbit CC2_M4_ACC18 = 0xFF22 ^ 11;
sbit CC2_M4_ACC19 = 0xFF22 ^ 15;
 sfr CC2_M5 = 0xFF24;
sbit CC2_M5_ACC20 = 0xFF24 ^ 3;
sbit CC2_M5_ACC21 = 0xFF24 ^ 7;
sbit CC2_M5_ACC22 = 0xFF24 ^ 11;
sbit CC2_M5_ACC23 = 0xFF24 ^ 15;
 sfr CC2_M6 = 0xFF26;
sbit CC2_M6_ACC24 = 0xFF26 ^ 3;
sbit CC2_M6_ACC25 = 0xFF26 ^ 7;
sbit CC2_M6_ACC26 = 0xFF26 ^ 11;
sbit CC2_M6_ACC27 = 0xFF26 ^ 15;
 sfr CC2_M7 = 0xFF28;
sbit CC2_M7_ACC28 = 0xFF28 ^ 3;
sbit CC2_M7_ACC29 = 0xFF28 ^ 7;
sbit CC2_M7_ACC30 = 0xFF28 ^ 11;
sbit CC2_M7_ACC31 = 0xFF28 ^ 15;
 sfr CC2_DRM = 0xFF2A;
 sfr CC2_OUT = 0xFF2C;
sbit CC2_OUT_CC0IO = 0xFF2C ^ 0;
sbit CC2_OUT_CC1IO = 0xFF2C ^ 1;
sbit CC2_OUT_CC2IO = 0xFF2C ^ 2;
sbit CC2_OUT_CC3IO = 0xFF2C ^ 3;
sbit CC2_OUT_CC4IO = 0xFF2C ^ 4;
sbit CC2_OUT_CC5IO = 0xFF2C ^ 5;
sbit CC2_OUT_CC6IO = 0xFF2C ^ 6;
sbit CC2_OUT_CC7IO = 0xFF2C ^ 7;
sbit CC2_OUT_CC8IO = 0xFF2C ^ 8;
sbit CC2_OUT_CC9IO = 0xFF2C ^ 9;
sbit CC2_OUT_CC10IO = 0xFF2C ^ 10;
sbit CC2_OUT_CC11IO = 0xFF2C ^ 11;
sbit CC2_OUT_CC12IO = 0xFF2C ^ 12;
sbit CC2_OUT_CC13IO = 0xFF2C ^ 13;
sbit CC2_OUT_CC14IO = 0xFF2C ^ 14;
sbit CC2_OUT_CC15IO = 0xFF2C ^ 15;



 sfr COMDATA = 0xF068;


 sfr CPUID = 0xF00C;
 sfr DPP0 = 0xFE00;
 sfr DPP1 = 0xFE02;
 sfr DPP2 = 0xFE04;
 sfr DPP3 = 0xFE06;
 sfr CSP = 0xFE08;
 sfr MDH = 0xFE0C;
 sfr MDL = 0xFE0E;
 sfr CP = 0xFE10;
 sfr SP = 0xFE12;
 sfr STKOV = 0xFE14;
 sfr STKUN = 0xFE16;
 sfr CPUCON1 = 0xFE18;
 sfr CPUCON2 = 0xFE1A;
 sfr MAL = 0xFE5C;
 sfr MAH = 0xFE5E;
 sfr IDX0 = 0xFF08;
 sfr IDX1 = 0xFF0A;
 sfr SPSEG = 0xFF0C;
 sfr MDC = 0xFF0E;
sbit MDC_MDRIU = 0xFF0E ^ 4;
 sfr PSW = 0xFF10;
sbit PSW_N = 0xFF10 ^ 0;
sbit PSW_C = 0xFF10 ^ 1;
sbit PSW_V = 0xFF10 ^ 2;
sbit PSW_Z = 0xFF10 ^ 3;
sbit PSW_E = 0xFF10 ^ 4;
sbit PSW_MULIP = 0xFF10 ^ 5;
sbit PSW_USR0 = 0xFF10 ^ 6;
sbit PSW_USR1 = 0xFF10 ^ 7;
sbit PSW_S1 = 0xFF10 ^ 10;
sbit PSW_IEN = 0xFF10 ^ 11;
 sfr VECSEG = 0xFF12;
 sfr ZEROS = 0xFF1C;
 sfr ONES = 0xFF1E;
 sfr MRW = 0xFFDA;
 sfr MCW = 0xFFDC;
sbit MCW_MS = 0xFFDC ^ 9;
sbit MCW_MP = 0xFFDC ^ 10;
 sfr MSW = 0xFFDE;
sbit MSW_MN = 0xFFDE ^ 8;
sbit MSW_MZ = 0xFFDE ^ 9;
sbit MSW_MC = 0xFFDE ^ 10;
sbit MSW_MSV = 0xFFDE ^ 11;
sbit MSW_ME = 0xFFDE ^ 12;
sbit MSW_MSL = 0xFFDE ^ 13;
sbit MSW_MV = 0xFFDE ^ 14;


 sfr GPT12E_T2 = 0xFE40;
 sfr GPT12E_T3 = 0xFE42;
 sfr GPT12E_T4 = 0xFE44;
 sfr GPT12E_T5 = 0xFE46;
 sfr GPT12E_T6 = 0xFE48;
 sfr GPT12E_CAPREL = 0xFE4A;
 sfr GPT12E_T2CON = 0xFF40;
sbit GPT12E_T2CON_T2R = 0xFF40 ^ 6;
sbit GPT12E_T2CON_T2UD = 0xFF40 ^ 7;
sbit GPT12E_T2CON_T2UDE = 0xFF40 ^ 8;
sbit GPT12E_T2CON_T2RC = 0xFF40 ^ 9;
sbit GPT12E_T2CON_T2IRDIS = 0xFF40 ^ 12;
sbit GPT12E_T2CON_T2EDGE = 0xFF40 ^ 13;
sbit GPT12E_T2CON_T2CHDIR = 0xFF40 ^ 14;
sbit GPT12E_T2CON_T2RDIR = 0xFF40 ^ 15;
 sfr GPT12E_T3CON = 0xFF42;
sbit GPT12E_T3CON_T3R = 0xFF42 ^ 6;
sbit GPT12E_T3CON_T3UD = 0xFF42 ^ 7;
sbit GPT12E_T3CON_T3UDE = 0xFF42 ^ 8;
sbit GPT12E_T3CON_T3OE = 0xFF42 ^ 9;
sbit GPT12E_T3CON_T3OTL = 0xFF42 ^ 10;
sbit GPT12E_T3CON_T3EDGE = 0xFF42 ^ 13;
sbit GPT12E_T3CON_T3CHDIR = 0xFF42 ^ 14;
sbit GPT12E_T3CON_T3RDIR = 0xFF42 ^ 15;
 sfr GPT12E_T4CON = 0xFF44;
sbit GPT12E_T4CON_T4R = 0xFF44 ^ 6;
sbit GPT12E_T4CON_T4UD = 0xFF44 ^ 7;
sbit GPT12E_T4CON_T4UDE = 0xFF44 ^ 8;
sbit GPT12E_T4CON_T4RC = 0xFF44 ^ 9;
sbit GPT12E_T4CON_T4IRDIS = 0xFF44 ^ 12;
sbit GPT12E_T4CON_T4EDGE = 0xFF44 ^ 13;
sbit GPT12E_T4CON_T4CHDIR = 0xFF44 ^ 14;
sbit GPT12E_T4CON_T4RDIR = 0xFF44 ^ 15;
 sfr GPT12E_T5CON = 0xFF46;
sbit GPT12E_T5CON_T5R = 0xFF46 ^ 6;
sbit GPT12E_T5CON_T5UD = 0xFF46 ^ 7;
sbit GPT12E_T5CON_T5UDE = 0xFF46 ^ 8;
sbit GPT12E_T5CON_T5RC = 0xFF46 ^ 9;
sbit GPT12E_T5CON_CT3 = 0xFF46 ^ 10;
sbit GPT12E_T5CON_T5CC = 0xFF46 ^ 11;
sbit GPT12E_T5CON_T5CLR = 0xFF46 ^ 14;
sbit GPT12E_T5CON_T5SC = 0xFF46 ^ 15;
 sfr GPT12E_T6CON = 0xFF48;
sbit GPT12E_T6CON_T6R = 0xFF48 ^ 6;
sbit GPT12E_T6CON_T6UD = 0xFF48 ^ 7;
sbit GPT12E_T6CON_T6UDE = 0xFF48 ^ 8;
sbit GPT12E_T6CON_T6OE = 0xFF48 ^ 9;
sbit GPT12E_T6CON_T6OTL = 0xFF48 ^ 10;
sbit GPT12E_T6CON_T6CLR = 0xFF48 ^ 14;
sbit GPT12E_T6CON_T6SR = 0xFF48 ^ 15;



 sfr CAN_1IC = 0xF142;
sbit CAN_1IC_IE = 0xF142 ^ 6;
sbit CAN_1IC_IR = 0xF142 ^ 7;
sbit CAN_1IC_GPX = 0xF142 ^ 8;
 sfr CAN_2IC = 0xF144;
sbit CAN_2IC_IE = 0xF144 ^ 6;
sbit CAN_2IC_IR = 0xF144 ^ 7;
sbit CAN_2IC_GPX = 0xF144 ^ 8;
 sfr CAN_3IC = 0xF146;
sbit CAN_3IC_IE = 0xF146 ^ 6;
sbit CAN_3IC_IR = 0xF146 ^ 7;
sbit CAN_3IC_GPX = 0xF146 ^ 8;
 sfr CAN_4IC = 0xF148;
sbit CAN_4IC_IE = 0xF148 ^ 6;
sbit CAN_4IC_IR = 0xF148 ^ 7;
sbit CAN_4IC_GPX = 0xF148 ^ 8;
 sfr CAN_5IC = 0xF14A;
sbit CAN_5IC_IE = 0xF14A ^ 6;
sbit CAN_5IC_IR = 0xF14A ^ 7;
sbit CAN_5IC_GPX = 0xF14A ^ 8;
 sfr CAN_6IC = 0xF14C;
sbit CAN_6IC_IE = 0xF14C ^ 6;
sbit CAN_6IC_IR = 0xF14C ^ 7;
sbit CAN_6IC_GPX = 0xF14C ^ 8;
 sfr CAN_7IC = 0xF14E;
sbit CAN_7IC_IE = 0xF14E ^ 6;
sbit CAN_7IC_IR = 0xF14E ^ 7;
sbit CAN_7IC_GPX = 0xF14E ^ 8;
 sfr ASC0_ABIC = 0xF15C;
sbit ASC0_ABIC_IE = 0xF15C ^ 6;
sbit ASC0_ABIC_IR = 0xF15C ^ 7;
sbit ASC0_ABIC_GPX = 0xF15C ^ 8;
 sfr CC2_CC16IC = 0xF160;
sbit CC2_CC16IC_IE = 0xF160 ^ 6;
sbit CC2_CC16IC_IR = 0xF160 ^ 7;
sbit CC2_CC16IC_GPX = 0xF160 ^ 8;
 sfr CC2_CC17IC = 0xF162;
sbit CC2_CC17IC_IE = 0xF162 ^ 6;
sbit CC2_CC17IC_IR = 0xF162 ^ 7;
sbit CC2_CC17IC_GPX = 0xF162 ^ 8;
 sfr CC2_CC18IC = 0xF164;
sbit CC2_CC18IC_IE = 0xF164 ^ 6;
sbit CC2_CC18IC_IR = 0xF164 ^ 7;
sbit CC2_CC18IC_GPX = 0xF164 ^ 8;
 sfr CC2_CC19IC = 0xF166;
sbit CC2_CC19IC_IE = 0xF166 ^ 6;
sbit CC2_CC19IC_IR = 0xF166 ^ 7;
sbit CC2_CC19IC_GPX = 0xF166 ^ 8;
 sfr CC2_CC20IC = 0xF168;
sbit CC2_CC20IC_IE = 0xF168 ^ 6;
sbit CC2_CC20IC_IR = 0xF168 ^ 7;
sbit CC2_CC20IC_GPX = 0xF168 ^ 8;
 sfr CC2_CC21IC = 0xF16A;
sbit CC2_CC21IC_IE = 0xF16A ^ 6;
sbit CC2_CC21IC_IR = 0xF16A ^ 7;
sbit CC2_CC21IC_GPX = 0xF16A ^ 8;
 sfr CC2_CC22IC = 0xF16C;
sbit CC2_CC22IC_IE = 0xF16C ^ 6;
sbit CC2_CC22IC_IR = 0xF16C ^ 7;
sbit CC2_CC22IC_GPX = 0xF16C ^ 8;
 sfr CC2_CC23IC = 0xF16E;
sbit CC2_CC23IC_IE = 0xF16E ^ 6;
sbit CC2_CC23IC_IR = 0xF16E ^ 7;
sbit CC2_CC23IC_GPX = 0xF16E ^ 8;
 sfr CC2_CC24IC = 0xF170;
sbit CC2_CC24IC_IE = 0xF170 ^ 6;
sbit CC2_CC24IC_IR = 0xF170 ^ 7;
sbit CC2_CC24IC_GPX = 0xF170 ^ 8;
 sfr CC2_CC25IC = 0xF172;
sbit CC2_CC25IC_IE = 0xF172 ^ 6;
sbit CC2_CC25IC_IR = 0xF172 ^ 7;
sbit CC2_CC25IC_GPX = 0xF172 ^ 8;
 sfr CC2_CC26IC = 0xF174;
sbit CC2_CC26IC_IE = 0xF174 ^ 6;
sbit CC2_CC26IC_IR = 0xF174 ^ 7;