📄 start_v2.a66
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; : = :
; 3 = 3 clock cycles
;
; WRPHF6: Phase F write clock cycle (TCONCS6.13 .. TCONCS6.14)
_WRPHF6 EQU 3 ; 0 = 0 clock cycles
; : = :
; 3 = 3 clock cycles
;
;
;
; ========== CONFIGURE EXTERNAL BUS BEHAVIOUR FOR CS7 AREA ===========
;
; --- Set CONFIG_CS7 = 1 to initialize the ADDRSEL7/FCONCS7/TCONCS7 registers
; --- Note: The CS7# chip default at reset allows to access the on-chip Twin-CAN
$SET (CONFIG_CS7 = 0)
;
; Definitions for Address Select register ADDRSEL7
; ================================================
;
_ADDR7 EQU 0x200000 ; Set CS7# Start Address (default 200000H)
;
_SIZE7 EQU 4*KB ; Set CS7# Size (default 1024*KB = 1*MB)
; possible values for _SIZE7 are:
; 4*KB (gives RGSZ1 = 0)
; 8*KB (gives RGSZ1 = 1)
; 16*KB (gives RGSZ1 = 2)
; 32*KB (gives RGSZ1 = 3)
; 64*KB (gives RGSZ1 = 4)
; 128*KB (gives RGSZ1 = 5)
; 256*KB (gives RGSZ1 = 6)
; 512*KB (gives RGSZ1 = 7)
; 1024*KB or 1*MB (gives RGSZ1 = 8)
; 2048*KB or 2*MB (gives RGSZ1 = 9)
; 4096*KB or 4*MB (gives RGSZ1 = 10)
; 8192*KB or 8*MB (gives RGSZ1 = 11)
; (RGSZ1 = 12 .. 15 reserved)
;
; Definitions for Function Configuration Register FCONCS7
; =======================================================
;
; ENCS7: Enable Chip Select (FCONCS7.0)
_ENCS7 EQU 1 ; 0 = Chip Select 0 disabled
; 1 = Chip Select 0 enabled
;
; RDYEN7: Ready Enable (FCONCS7.1)
_RDYEN7 EQU 1 ; 0 = Access time controlled by TCONCS7.PHE7
; 1 = Access time cont. by TCONCS7.PHE7 and READY signal
;
; RDYMOD7: Ready Mode (FCONCS7.2)
_RDYMOD7 EQU 1 ; 0 = Asynchronous READY
; 1 = Synchronous READY
;
; BTYP7: Bus Type Selection (FCONCS7.4 .. FCONCS7.5)
_BTYP7 EQU 2 ; 0 = 8 bit Demultiplexed bus
; 1 = 8 bit Multiplexed bus
; 2 = 16 bit Demultiplexed bus
; 3 = 16 bit Multiplexed bus
;
;
; TCONCS7: Definitions for the Timing Configuration register
; ==========================================================
;
; PHA7: Phase A clock cycle (TCONCS7.0 .. TCONCS7.1)
_PHA7 EQU 0 ; 0 = 0 clock cycles
; : = :
; 3 = 3 clock cycles
;
; PHB7: Phase B clock cycle (TCONCS7.2)
_PHB7 EQU 0 ; 0 = 1 clock cycle
; 1 = 2 clock cycles
;
; PHC7: Phase C clock cycle (TCONCS7.3 .. TCONCS7.4)
_PHC7 EQU 0 ; 0 = 0 clock cycles
; : = :
; 3 = 3 clock cycles
;
; PHD7: Phase D clock cycle (TCONCS7.5)
_PHD7 EQU 0 ; 0 = 0 clock cycles
; 1 = 1 clock cycle
;
; PHE7: Phase E clock cycle (TCONCS7.6 .. TCONCS7.10)
_PHE7 EQU 0 ; 0 = 1 clock cycle
; : = :
; 31 = 32 clock cycles
;
; RDPHF7: Phase F read clock cycle (TCONCS7.11 .. TCONCS7.12)
_RDPHF7 EQU 0 ; 0 = 0 clock cycles
; : = :
; 3 = 3 clock cycles
;
; WRPHF7: Phase F write clock cycle (TCONCS7.13 .. TCONCS7.14)
_WRPHF7 EQU 0 ; 0 = 0 clock cycles
; : = :
; 3 = 3 clock cycles
;
;------------------------------------------------------------------------------
$IF TINY
$SET (DPPUSE = 0)
$ENDIF
$IF NOT TINY
ASSUME DPP3:SYSTEM
ASSUME DPP2:NDATA
$ENDIF
NAME ?C_STARTUP
PUBLIC ?C_STARTUP
PUBLIC ?L?VECSC
?L?VECSC EQU _VECSC ; Interrupt Vector Spacing for L166
$IF MEDIUM OR LARGE OR HLARGE OR XLARGE
Model LIT 'FAR'
$ELSE
Model LIT 'NEAR'
$ENDIF
EXTRN main:Model
PUBLIC ?C_USRSTKBOT
?C_USERSTACK SECTION DATA PUBLIC 'NDATA'
$IF NOT TINY
NDATA DGROUP ?C_USERSTACK
$ENDIF
?C_USRSTKBOT:
DS USTSZ ; Size of User Stack
?C_USERSTKTOP:
?C_USERSTACK ENDS
?C_MAINREGISTERS REGDEF R0 - R15
?C_SYSSTACK SECTION DATA PUBLIC 'IDATA'
$IF NOT TINY
SDATA DGROUP ?C_SYSSTACK
$ENDIF
_BOS: ; bottom of system stack
DS SSTSZ ; Size of User Stack
_TOS: ; top of system stack
?C_SYSSTACK ENDS
PUBLIC ?C_SYSSTKBOT
PUBLIC ?C_SYSSTKTOP
?C_SYSSTKBOT EQU _BOS
?C_SYSSTKTOP EQU _TOS
SSKDEF 7 ; unlimited System stack size
?C_STARTUP_CODE SECTION CODE 'ICODE'
;------------------------------------------------------------------------------
; Special Function Register Addresses
ADDRSEL1 EQU 0EE1EH
ADDRSEL2 EQU 0EE26H
ADDRSEL3 EQU 0EE2EH
ADDRSEL4 EQU 0EE36H
ADDRSEL5 EQU 0EE3EH
ADDRSEL6 EQU 0EE46H
ADDRSEL7 EQU 0EE4EH
CPUCON1 DEFR 0FE18H
CPUCON2 DEFR 0FE1AH
EBCMOD0 EQU 0EE00H
EBCMOD1 EQU 0EE02H
FOCON DEFR 0FFAAH
FCONCS0 EQU 0EE12H
FCONCS1 EQU 0EE1AH
FCONCS2 EQU 0EE22H
FCONCS3 EQU 0EE2AH
FCONCS4 EQU 0EE32H
FCONCS5 EQU 0EE3AH
FCONCS6 EQU 0EE42H
FCONCS7 EQU 0EE4AH
RSTCON EQU 0F1E0H
SP DEFR 0FE12H
SPSEG DEFR 0FF0CH
STKOV DEFR 0FE14H
STKUN DEFR 0FE16H
SYSCON1 DEFR 0F1DCH
SYSCON3 DEFR 0F1D4H
PLLCON DEFR 0F1D0H
TCONCS0 EQU 0EE10H
TCONCS1 EQU 0EE18H
TCONCS2 EQU 0EE20H
TCONCS3 EQU 0EE28H
TCONCS4 EQU 0EE30H
TCONCS5 EQU 0EE38H
TCONCS6 EQU 0EE40H
TCONCS7 EQU 0EE48H
WDTCON DEFR 0FFAEH
; Macro for calculation of ADDRSEL values -------------
CALC_ADDRSEL MACRO sym, adr, size
IF size <= (4*KB)
sym EQU ((adr >> 8) AND 0xFFF0) OR 0
ELSEIF size <= (8*KB)
sym EQU ((adr >> 8) AND 0xFFE0) OR 1
ELSEIF size <= (16*KB)
sym EQU ((adr >> 8) AND 0xFFC0) OR 2
ELSEIF size <= (32*KB)
sym EQU ((adr >> 8) AND 0xFF80) OR 3
ELSEIF size <= (64*KB)
sym EQU ((adr >> 8) AND 0xFF00) OR 4
ELSEIF size <= (128*KB)
sym EQU ((adr >> 8) AND 0xFE00) OR 5
ELSEIF size <= (256*KB)
sym EQU ((adr >> 8) AND 0xFC00) OR 6
ELSEIF size <= (512*KB)
sym EQU ((adr >> 8) AND 0xF800) OR 7
ELSEIF size <= (1*MB)
sym EQU ((adr >> 8) AND 0xF000) OR 8
ELSEIF size <= (2*MB)
sym EQU ((adr >> 8) AND 0xE000) OR 9
ELSEIF size <= (4*MB)
sym EQU ((adr >> 8) AND 0xC000) OR 10
ELSEIF size <= (8*MB)
sym EQU ((adr >> 8) AND 0x8000) OR 11
ENDIF
ENDM
; -----------------------------------------------------
?C_RESET PROC TASK C_STARTUP INTNO RESET = 0
?C_STARTUP: LABEL Model
$IF (WATCHDOG = 0)
DISWDT ; Disable watchdog timer
$ELSE
_WDTCON SET (_WDTREL << 8) OR (_WDTIN)
MOV WDTCON,#_WDTCON ; Set WDTCON register
SRVWDT ; Enable watchdog
$ENDIF
; Set CPUCON1 register
_CPC1 SET (_VECSC<<5) OR (_WDTCTL<<4) OR (_SGTDIS<<3)
_CPC1 SET _CPC1 OR (_INTSCXT<<2) OR (_BP<<1) OR (_ZCJ)
MOV CPUCON1,#_CPC1
$IF (INIT_CPUCON2 = 1) ; Set CPUCON2 register
_CPC2 SET (_RETST<<3) OR (_FASTBL<<2) OR (_FASTPEC<<1) OR (_SL)
_CPC2 SET _CPC2 OR (_EIOIAEN<<7) OR (_STEN<<6) OR (_ZSC<<5) OR (_OVRUN<<4)
_CPC2 SET _CPC2 OR (_BYPPF<<9) OR (_BYPF<<8)
_CPC2 SET _CPC2 OR (_FIFODEPTH<<12) OR (_FIFOFED<<10)
MOV CPUCON2,#_CPC2
$ENDIF
$IF (INIT_SYSCON3 = 1) ; Set SYSCON1 register
_SYSC1 SET (_CPSYS<<8) OR (_PFCFG<<4) OR (_PDCFG<<2) OR (_SLEEPCON)
EXTR #01H ; Extended SFR access
MOV SYSCON1,#_SYSC1
$ENDIF
$IF (INIT_SYSCON3 = 1) ; Set SYSCON3 register
_SYSC3 SET ADCDIS OR (ASC0DIS << 1) OR (SSC0DIS << 2) OR (GPTDIS << 3)
_SYSC3 SET _SYSC3 OR (FMDIS << 5) OR (CC1DIS << 6) OR (CC2DIS << 7)
_SYSC3 SET _SYSC3 OR (CC6DIS << 8) OR (ASC1DIS << 10) OR (I2CDIS << 11)
_SYSC3 SET _SYSC3 OR (SDLMDIS << 12) OR (CANDIS << 13) OR (SSC1DIS<< 15)
EXTR #1
MOV SYSCON3,#_SYSC3
$ENDIF
$IF (CONFIG_EBC = 1) ; Set EBCMOD0 register
_EBC0 SET (_SLAVE<<9) OR (_ARBEN<<8) OR (_CSPEN<<4) OR (_SAPEN)
_EBC0 SET _EBC0 OR (_BYTDIS<<12) OR (_WRCFG<<11) OR (_EBCDIS<<10)
_EBC0 SET _EBC0 OR (_RDYPOL<<15) OR (_RDYDIS<<14) OR (_ALEDIS<<13)
MOV R0,#_EBC0
MOV EBCMOD0,R0
; Set EBCMOD1 register
_EBC1 SET (_DHPDIS<<6) OR (_APDIS)
MOV R0,#_EBC1
MOV EBCMOD1,R0
$ENDIF
$IF (CONFIG_CS0)
; Set TCONCS0 register
_TCS0 SET (_PHD0<<5) OR (_PHC0<<3) OR (_PHB0<<2) OR (_PHA0)
_TCS0 SET _TCS0 OR (_WRPHF0<<13) OR (_RDPHF0<<11) OR (_PHE0<<6)
MOV R0,#_TCS0
MOV TCONCS0,R0
; Set FCONCS0 register
_FCS0 SET (_BTYP0<<4) OR (_RDYMOD0<<2) OR (_RDYEN0<<1) OR (_ENCS0)
MOV R0,#_FCS0
MOV FCONCS0,R0
$ENDIF
$IF (CONFIG_CS1)
; Set TCONCS1 register
_TCS1 SET (_PHD1<<5) OR (_PHC1<<3) OR (_PHB1<<2) OR (_PHA1)
_TCS1 SET _TCS1 OR (_WRPHF1<<13) OR (_RDPHF1<<11) OR (_PHE1<<6)
MOV R0,#_TCS1
MOV TCONCS1,R0
; Set ADDRSEL1 register
CALC_ADDRSEL _ADDRSEL1, _ADDR1, _SIZE1
MOV R0,#_ADDRSEL1
MOV ADDRSEL1,R0
; Set FCONCS1 register
_FCS1 SET (_BTYP1<<4) OR (_RDYMOD1<<2) OR (_RDYEN1<<1) OR (_ENCS1)
MOV R0,#_FCS1
MOV FCONCS1,R0
$ENDIF
$IF (CONFIG_CS2)
; Set TCONCS2 register
_TCS2 SET (_PHD2<<5) OR (_PHC2<<3) OR (_PHB2<<2) OR (_PHA2)
_TCS2 SET _TCS2 OR (_WRPHF2<<13) OR (_RDPHF2<<11) OR (_PHE2<<6)
MOV R0,#_TCS2
MOV TCONCS2,R0
; Set ADDRSEL2 register
CALC_ADDRSEL _ADDRSEL2, _ADDR2, _SIZE2
MOV R0,#_ADDRSEL2
MOV ADDRSEL2,R0
; Set FCONCS2 register
_FCS2 SET (_BTYP2<<4) OR (_RDYMOD2<<2) OR (_RDYEN2<<1) OR (_ENCS2)
MOV R0,#_FCS2
MOV FCONCS2,R0
$ENDIF
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