📄 start_v2.a66
字号:
; FORV: Frequency Output Reload Value (FOCON.8 .. FOCON.13)
_FORV EQU 0 ; is copied to FOCNT upon each underflow of FOCNT
;
; FOSS: Frequency Output Signal Select (FOCON.14)
_FOSS EQU 0 ; 0 = Output of the toggle latch; 0.5 duty cycle
; 1 = Output of reload counter; duty cycle depends on FORV
;
; FOEN: Frequency Output Enable (FOCON.15)
_FOEN EQU 0 ; 0 = P3.15 is IO pin when _CLKEN is 0
; 1 = P3.15 outputs f_OUT when _CLKEN is 0
;
;
; ============= CONFIGURE EXTERNAL BUS (EBC) BEHAVIOUR =====================
;
; --- Set CONFIG_EBC = 1 to initialize the EBCMOD0/EBCMOD1 registers
$SET (CONFIG_EBC = 1) ; 0 = EBCMOD0/EBCMOD1 are set during reset according the
; of configuration bus (typical Port0) values.
; 1 = the following external bus configuration values
; are written to EBCMOD and BUSACT0
;
; Definitions for EBC Mode 0 register EBCMOD0
; ===========================================
;
; SAPEN: Segment Address Pins Enabled (EBCMOD0.0 .. EBCMOD0.3)
_SAPEN EQU 4 ; 0 = No segment address pins enabled
; 1 = One (A16) segment address pin enabled
; : = :
; 8 = Eight (A16 .. A23) address pins enabled
; 9 - 15 = reserved
;
; CSPEN: CSx Pins Enabled (EBCMOD0.4 .. EBCMOD0.7)
_CSPEN EQU 8 ; 0 = No CS pins enabled
; 1 = One CS (CS0) pin enabled
; : = :
; 8 = Eight CS (CS0 .. CS7) pins enabled
; 9 - 15 = reserved
; Note: the number of available CS pins depends on the chip used
;
; ARBEN: Bus Arbitration Pins Enabled (EBCMOD0.8)
_ARBEN EQU 0 ; 0 = HOLD, HLDA and BREQ pins are tristate or act as GPIO
; 1 = HOLD, HLDA and BREQ pins act normally
;
; SLAVE: SLAVE mode enable (EBCMOD0.9)
_SLAVE EQU 0 ; 0 = Bus arbiter acts in master mode
; 1 = Bus arbiter acts in slave mode
;
; EBCDIS: EBC pins disable (EBCMOD0.10)
_EBCDIS EQU 0 ; 0 = EBC is using the pins for external bus
; 1 = EBC off (pins to be used as GPIO if implemented)
;
; WRCFG: Configuration for pins WR/WRL and BHE/WRH (EBCMOD0.11)
_WRCFG EQU 0 ; 0 = Pins act as WR and BHE
; 1 = Pins act as WRL and WRH
;
; BYTDIS: BHE pin disable (EBCMOD0.12)
_BYTDIS EQU 0 ; 0 = BHE enabled
; 1 = BHE disabled (GPIO function if implemented)
;
; ALEDIS: ALE pin disable (EBCMOD0.13)
_ALEDIS EQU 0 ; 0 = ALE pin enabled
; 1 = ALE pin disabled (GPIO function if implemented)
;
; RDYDIS: READY pin disable (EBCMOD0.14)
_RDYDIS EQU 0 ; 0 = READY enabled
; 1 = READY disabled (GPIO function if implemented)
;
; RDYPOL: READY pin polarity (EBCMOD0.15)
_RDYPOL EQU 0 ; 0 = READY pin is active low
; 1 = READY pin is active high
;
;
;
; Definitions for EBC Mode 1 register EBCMOD1
; ===========================================
;
; APDIS: Address Port Pins Disable (EBCMOD1.0 .. EBCMOD0.4)
_APDIS EQU 0 ; 0 = Address port PORT1 used as address bus
; 1 - 30 = reserved
; 31 = Address bus disabled (PORT1 used as GPIO)
;
; DHPDIS: Data High Port Pins Disable (EBCMOD1.6)
_DHPDIS EQU 0 ; 0 = Data bus pins 15-8 of PORT0 enabled
; 1 = Data bus pins 15-8 disabled (used as GPIO)
;
;
;
; ========== CONFIGURE EXTERNAL BUS BEHAVIOUR FOR CS0 AREA ===========
;
; --- Set CONFIG_CS0 = 1 to initialize the FCONCS0/TCONCS0 registers
$SET (CONFIG_CS0 = 1)
;
; Definitions for Function Configuration Register FCONCS0
; =======================================================
;
; ENCS0: Enable Chip Select (FCONCS0.0)
_ENCS0 EQU 1 ; 0 = Chip Select 0 disabled
; 1 = Chip Select 0 enabled
;
; RDYEN0: Ready Enable (FCONCS0.1)
_RDYEN0 EQU 0 ; 0 = Access time controlled by TCONCS0.PHE0
; 1 = Access time cont. by TCONCS0.PHE0 and READY signal
;
; RDYMOD0: Ready Mode (FCONCS0.2)
_RDYMOD0 EQU 0 ; 0 = Asynchronous READY
; 1 = Synchronous READY
;
; BTYP0: Bus Type Selection (FCONCS0.4 .. FCONCS0.5)
_BTYP0 EQU 2 ; 0 = 8 bit Demultiplexed bus
; 1 = 8 bit Multiplexed bus
; 2 = 16 bit Demultiplexed bus
; 3 = 16 bit Multiplexed bus
;
;
; TCONCS0: Definitions for the Timing Configuration register
; ==========================================================
;
; PHA0: Phase A clock cycle (TCONCS0.0 .. TCONCS0.1)
_PHA0 EQU 0 ; 0 = 0 clock cycles
; : = :
; 3 = 3 clock cycles
;
; PHB0: Phase B clock cycle (TCONCS0.2)
_PHB0 EQU 1 ; 0 = 1 clock cycle
; 1 = 2 clock cycles
;
; PHC0: Phase C clock cycle (TCONCS0.3 .. TCONCS0.4)
_PHC0 EQU 0 ; 0 = 0 clock cycles
; : = :
; 3 = 3 clock cycles
;
; PHD0: Phase D clock cycle (TCONCS0.5)
_PHD0 EQU 1 ; 0 = 0 clock cycles
; 1 = 1 clock cycle
;
; PHE0: Phase E clock cycle (TCONCS0.6 .. TCONCS0.10)
_PHE0 EQU 1 ; 0 = 1 clock cycle
; : = :
; 31 = 32 clock cycles
;
; RDPHF0: Phase F read clock cycle (TCONCS0.11 .. TCONCS0.12)
_RDPHF0 EQU 2 ; 0 = 0 clock cycles
; : = :
; 3 = 3 clock cycles
;
; WRPHF0: Phase F write clock cycle (TCONCS0.13 .. TCONCS0.14)
_WRPHF0 EQU 2 ; 0 = 0 clock cycles
; : = :
; 3 = 3 clock cycles
;
;
; ========== CONFIGURE EXTERNAL BUS BEHAVIOUR FOR CS1 AREA ===========
;
; --- Set CONFIG_CS1 = 1 to initialize the ADDRSEL1/FCONCS1/TCONCS1 registers
$SET (CONFIG_CS1 = 0)
;
; Definitions for Address Select register ADDRSEL1
; ================================================
;
_ADDR1 EQU 0x400000 ; Set CS1# Start Address (default 100000H)
;
_SIZE1 EQU 256*KB ; Set CS1# Size (default 1024*KB = 1*MB)
; possible values for _SIZE1 are:
; 4*KB (gives RGSZ1 = 0)
; 8*KB (gives RGSZ1 = 1)
; 16*KB (gives RGSZ1 = 2)
; 32*KB (gives RGSZ1 = 3)
; 64*KB (gives RGSZ1 = 4)
; 128*KB (gives RGSZ1 = 5)
; 256*KB (gives RGSZ1 = 6)
; 512*KB (gives RGSZ1 = 7)
; 1024*KB or 1*MB (gives RGSZ1 = 8)
; 2048*KB or 2*MB (gives RGSZ1 = 9)
; 4096*KB or 4*MB (gives RGSZ1 = 10)
; 8192*KB or 8*MB (gives RGSZ1 = 11)
; (RGSZ1 = 12 .. 15 reserved)
;
; Definitions for Function Configuration Register FCONCS1
; =======================================================
;
; ENCS1: Enable Chip Select (FCONCS1.0)
_ENCS1 EQU 1 ; 0 = Chip Select 0 disabled
; 1 = Chip Select 0 enabled
;
; RDYEN1: Ready Enable (FCONCS1.1)
_RDYEN1 EQU 0 ; 0 = Access time controlled by TCONCS1.PHE1
; 1 = Access time cont. by TCONCS1.PHE1 and READY signal
;
; RDYMOD1: Ready Mode (FCONCS1.2)
_RDYMOD1 EQU 0 ; 0 = Asynchronous READY
; 1 = Synchronous READY
;
; BTYP1: Bus Type Selection (FCONCS1.4 .. FCONCS1.5)
_BTYP1 EQU 2 ; 0 = 8 bit Demultiplexed bus
; 1 = 8 bit Multiplexed bus
; 2 = 16 bit Demultiplexed bus
; 3 = 16 bit Multiplexed bus
;
;
; TCONCS1: Definitions for the Timing Configuration register
; ==========================================================
;
; PHA1: Phase A clock cycle (TCONCS1.0 .. TCONCS1.1)
_PHA1 EQU 0 ; 0 = 0 clock cycles
; : = :
; 3 = 3 clock cycles
;
; PHB1: Phase B clock cycle (TCONCS1.2)
_PHB1 EQU 0 ; 0 = 1 clock cycle
; 1 = 2 clock cycles
;
; PHC1: Phase C clock cycle (TCONCS1.3 .. TCONCS1.4)
_PHC1 EQU 0 ; 0 = 0 clock cycles
; : = :
; 3 = 3 clock cycles
;
; PHD1: Phase D clock cycle (TCONCS1.5)
_PHD1 EQU 0 ; 0 = 0 clock cycles
; 1 = 1 clock cycle
;
; PHE1: Phase E clock cycle (TCONCS1.6 .. TCONCS1.10)
_PHE1 EQU 9 ; 0 = 1 clock cycle
; : = :
; 31 = 32 clock cycles
;
; RDPHF1: Phase F read clock cycle (TCONCS1.11 .. TCONCS1.12)
_RDPHF1 EQU 0 ; 0 = 0 clock cycles
; : = :
; 3 = 3 clock cycles
;
; WRPHF1: Phase F write clock cycle (TCONCS1.13 .. TCONCS1.14)
_WRPHF1 EQU 3 ; 0 = 0 clock cycles
; : = :
; 3 = 3 clock cycles
;
;
;
; ========== CONFIGURE EXTERNAL BUS BEHAVIOUR FOR CS2 AREA ===========
;
; --- Set CONFIG_CS2 = 1 to initialize the ADDRSEL2/FCONCS2/TCONCS2 registers
$SET (CONFIG_CS2 = 0)
;
; Definitions for Address Select register ADDRSEL2
; ================================================
;
_ADDR2 EQU 0x200000 ; Set CS2# Start Address (default 200000H)
;
_SIZE2 EQU 1*MB ; Set CS2# Size (default 1024*KB = 1*MB)
; possible values for _SIZE2 are:
; 4*KB (gives RGSZ1 = 0)
; 8*KB (gives RGSZ1 = 1)
; 16*KB (gives RGSZ1 = 2)
; 32*KB (gives RGSZ1 = 3)
; 64*KB (gives RGSZ1 = 4)
; 128*KB (gives RGSZ1 = 5)
; 256*KB (gives RGSZ1 = 6)
; 512*KB (gives RGSZ1 = 7)
; 1024*KB or 1*MB (gives RGSZ1 = 8)
; 2048*KB or 2*MB (gives RGSZ1 = 9)
; 4096*KB or 4*MB (gives RGSZ1 = 10)
; 8192*KB or 8*MB (gives RGSZ1 = 11)
; (RGSZ1 = 12 .. 15 reserved)
;
; Definitions for Function Configuration Register FCONCS2
; =======================================================
;
; ENCS2: Enable Chip Select (FCONCS2.0)
_ENCS2 EQU 1 ; 0 = Chip Select 0 disabled
; 1 = Chip Select 0 enabled
;
; RDYEN2: Ready Enable (FCONCS2.1)
_RDYEN2 EQU 0 ; 0 = Access time controlled by TCONCS2.PHE2
; 1 = Access time cont. by TCONCS2.PHE2 and READY signal
;
; RDYMOD2: Ready Mode (FCONCS2.2)
_RDYMOD2 EQU 0 ; 0 = Asynchronous READY
; 1 = Synchronous READY
;
; BTYP2: Bus Type Selection (FCONCS2.4 .. FCONCS2.5)
_BTYP2 EQU 2 ; 0 = 8 bit Demultiplexed bus
; 1 = 8 bit Multiplexed bus
; 2 = 16 bit Demultiplexed bus
; 3 = 16 bit Multiplexed bus
;
;
; TCONCS2: Definitions for the Timing Configuration register
; ==========================================================
;
; PHA2: Phase A clock cycle (TCONCS2.0 .. TCONCS2.1)
_PHA2 EQU 0 ; 0 = 0 clock cycles
; : = :
; 3 = 3 clock cycles
;
; PHB2: Phase B clock cycle (TCONCS2.2)
_PHB2 EQU 0 ; 0 = 1 clock cycle
; 1 = 2 clock cycles
;
; PHC2: Phase C clock cycle (TCONCS2.3 .. TCONCS2.4)
_PHC2 EQU 0 ; 0 = 0 clock cycles
; : = :
; 3 = 3 clock cycles
;
; PHD2: Phase D clock cycle (TCONCS2.5)
_PHD2 EQU 0 ; 0 = 0 clock cycles
; 1 = 1 clock cycle
;
; PHE2: Phase E clock cycle (TCONCS2.6 .. TCONCS2.10)
_PHE2 EQU 9 ; 0 = 1 clock cycle
; : = :
; 31 = 32 clock cycles
;
; RDPHF2: Phase F read clock cycle (TCONCS2.11 .. TCONCS2.12)
_RDPHF2 EQU 0 ; 0 = 0 clock cycles
; : = :
; 3 = 3 clock cycles
;
; WRPHF2: Phase F write clock cycle (TCONCS2.13 .. TCONCS2.14)
_WRPHF2 EQU 3 ; 0 = 0 clock cycles
; : = :
; 3 = 3 clock cycles
;
;
;
; ========== CONFIGURE EXTERNAL BUS BEHAVIOUR FOR CS3 AREA ===========
;
; --- Set CONFIG_CS3 = 1 to initialize the ADDRSEL3/FCONCS3/TCONCS3 registers
$SET (CONFIG_CS3 = 0)
;
; Definitions for Address Select register ADDRSEL3
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -