start_v2.a66

这个文件是西门子16位单片机从c166上的一些应用程序的源代码

$MODV2                                  ; Define C166v2 core mode
;
;------------------------------------------------------------------------------
;  This file is part of the C166 Compiler package
;  Copyright KEIL ELEKTRONIK GmbH 1993 - 2004
;  Version 4.04b
;  Note:  PHAx default set to 0 as bypass for TwinCAN device problem.
;------------------------------------------------------------------------------
;  START_V2.A66:  This code is executed after processor reset and provides the
;                 startup sequence for the C166v2/Super10 architecture CPU's.
;                 (i.e. XC161, XC164, XC167, ect.)
;
;  You may add this file to a uVision2 project - in this case it will be 
;  automatically assembled and linked.
;
;  For manual translation of this file use A166 with the following invocation:
;
;     A166 START_V2.A66 SET (<model>)
;
;     <model> determines the memory model and can be one of the following:
;         TINY, SMALL, COMPACT, HCOMPACT, MEDIUM, LARGE, HLARGE, XLARGE
;
;  Example:  A166 START_V2.A66 SET (SMALL)
;
;  For manual linkage of the modified START_V2.OBJ file to your application
;  use the following L166 invocation:
;
;     L166 <your object file list>, START_V2.OBJ <controls>
;
;------------------------------------------------------------------------------
; Setup model-dependend Assembler controls
$CASE
$IF NOT TINY
$SEGMENTED
$ENDIF
; Settings for ADDRSEL calculation (do not change!)
KB          EQU    0x400     ; define KB constant for CS _SIZE calculation
MB          EQU    0x400*KB  ; define MB as 1024KB
;------------------------------------------------------------------------------
;
; Definitions for System and User Stack
; =====================================
;
; STKSZ: Maximum System Stack Size selection
;  Defines the system stack space that is used by CALL/RET and PUSH/POP 
;  instructions.  The system stack space must be adjusted according the actual
;  requirements of the application.
SSTSZ   EQU     0x200    ; set System Stack Size to 200H Bytes
;
; USTSZ: User Stack Size Definition 
;  Defines the user stack space available for automatics.  This stack space is
;  accessed by R0.  The user stack space must be adjusted according the actual
;  requirements of the application.
USTSZ   EQU     0x1000   ; set User Stack Size to 1000H Bytes.
;
;
; Definitions for Startup Code
; ============================
;
; CLR_MEMORY: Disable Memory Zero Initialization of RAM area
; --- Set CLR_MEMORY = 0 to disable memory zero initilization
$SET (CLR_MEMORY = 1)
;
; INIT_VARS: Disable Variable Initialization
; --- Set INIT_VARS = 0 to disable variable initilization
$SET (INIT_VARS = 1)
;
; DPPUSE:  Re-assign DPP registers
; --- Set DPPUSE = 0 to reduce the code size of the startup code, if you
;                    are not using the L166 DPPUSE directive.
$SET (DPPUSE = 1)
;
; DPP3USE: Use DPP3 register during variable initilization
; --- Set DPP3USE = 0 to disable the usage of DPP3 during initilization of
;                     variables.  This option might be required if you write
;                     program parts that are reloaded during application 
;                     execution and increase code size of the startup code.
$SET (DPP3USE = 1)
;
;
; Definitions for Cpu Configuration Register CPUCON1
; ==================================================
;
; ZCJ: Zero Cycle Jump Function (CPUCON1.0):
_ZCJ     EQU    0       ; 0 = Disable Zero Cycle Jump Function
                        ; 1 = Enable Zero Cycle Jump Function
;
; BP: Branch Prediction Unit (CPUCON1.1):
_BP      EQU    0       ; 0 = Disable Branch Prediction Unit
                        ; 1 = Enable Branch Prediction Unit
;
; INTSCXT: Interruptability of Switch Context Instruction (CPUCON1.2):
_INTSCXT EQU    0       ; 0 = Disable Interruption of SCXT instruction
                        ; 1 = Enable Interruption of SCXT instruction
;
; SGTDIS: Disable Segmentation Control (CPUCON1.3):
$IF TINY
_SGTDIS  EQU    1       ; disable segmented mode for TINY model
$ELSE
_SGTDIS  EQU    0       ; enable segmented mode (Reset Value)
$ENDIF
;
; WDTCTL: Watchdog Timer Control (CPUCON1.4):
_WDTCTL  EQU    0       ; 0 = DISWDT executable until end of EINIT
                        ; 1 = DISWDT/ENWDT always executable
;
; VECSC: Vector Table Scaling Factor (CPUCON1.5 .. CPUCON1.6)
_VECSC   EQU    0       ; 0 = Space between two vectors is 2 words
                        ; 1 = Space between two vectors is 4 words
                        ; 2 = Space between two vectors is 8 words
                        ; 3 = Space between two vectors is 16 words
;
;
; Definitions for CPU Configuration Register CPUCON2
; ==================================================
;
; INIT_CPUCON2: Init CPUCON2 register
; --- Set INIT_CPUCON2 = 1 to initilize the SYSCON1 register
$SET (INIT_CPUCON2 = 0) ; default: do not initilize CPUCON2  
;
; SL: Short Loop Mode (CPUCON2.0)
_SL       EQU   1       ; 0 = Short Loop mode disabled
                        ; 1 = Short Loop mode enabled
;
; FASTPEC: Fast Pec Event Injection (CPUCON2.1)
_FASTPEC  EQU   1       ; 0 = Direct Injection of PEC Events disabled
                        ; 1 = Direct Injection of PEC Events enabled
;
; FASTBL: Fast Block Transfer Injection (CPUCON2.2)
_FASTBL   EQU   0       ; 0 = Direct Injection for Block Transfers disabled
                        ; 1 = Direct Injection for Block Transfers enabled
;
; RETST: Return Stack (CPUCON2.3)
_RETST    EQU   1       ; 0 = Return Stack disabled
                        ; 1 = Return Stack enabled
;
; OVRUN: Pipeline Bubble Overrun (CPUCON2.4)
_OVRUN    EQU   1       ; 0 = Overrun of Pipeline Bubbles not allowed
                        ; 1 = Overrun of Pipeline Bubbles allowed
;
; ZSC: Zero Cycle Jump Cache (CPUCON2.5)
_ZSC      EQU   1       ; 0 = Zero Cycle Jump Cache disabled
                        ; 1 = Zero Cycle Jump Cache enabled
;
; STEN: Stall Instruction (CPUCON2.6)
_STEN     EQU   0       ; 0 = Stall instruction disabled
                        ; 1 = Stall instruction enabled
;
; EIOIAEN: Early IO Injection Acknowledge
_EIOIAEN  EQU   1       ; 0 = Injection ack. by destructive read not guaranteed
;                       ; 1 = Injection ack. by destructive read guaranteed
; 
; BYPF: Fetch Bypass Control (CPUCON2.8)
_BYPF     EQU   1       ; 0 = Bypass Path from Fetch to Decode disabled
                        ; 1 = Bypass Path from Fetch to Decode enabled
;
; BYPPF: Prefecth Bypass Control (CPUCON2.9)
_BYPPF    EQU   1       ; 0 = Bypass Path from Prefetch to Decode disabled
                        ; 1 = Bypass Path from Prefetch to Decode enabled
;
; FIFOFED: FIFO Fill Configuration (CPUCON2.10 .. CPUCON2.11)
_FIFOFED  EQU   3       ; 0 = FIFO disabled
                        ; 1 = FIFO filled with up to 1 instruction per cycle
                        ; 2 = FIFO filled with up to 2 instructions per cycle
                        ; 3 = FIFO filled with up to 3 instructions per cycle
;
; FIFODEPTH: FIFO Depth Configuration (CPUCON2.12 .. CPUCON2.15)
_FIFODEPTH EQU  8       ; 0 = No FIFO entries (No FIFO)
                        ; 1 = 1 FIFO entry
                        ; ...
                        ; 8 = 8 FIFO entries
                        ; 9 - 15 = reserved
;
; Definitions for System Configuration Register SYSCON1
; =====================================================
;
; INIT_SYSCON1: Init SYSCON1 register
; --- Set INIT_SYSCON1 = 1 to initilize the SYSCON1 register
$SET (INIT_SYSCON1 = 0)
;
; SLEEPCON: Sleep Mode Configuration (SYSCON1.0 .. SYSCON1.1)
_SLEEPCON EQU    0      ; 0 = Normal IDLE mode entered upone IDLE instruction
                        ; 1 = SLEEP mode entered upone IDLE instruction
                        ; 2 - 3 = reserved
;
; PDCFG: Port Driver Configuration (SYSCON1.2 .. SYSCON1.3)
_PDCFG    EQU    0      ; 0 = Port drivers are always ON (default)
                        ; 1 = Port drivers are off in IDLE or Sleep mode
                        ; 2 = Port drivers are off in Powerdown mode
                        ; 3 = reserved
;
; PFCFG: Program Flash Configuration (SYSCON1.4 .. SYSCON1.5)
_PFCFG    EQU    0      ; 0 = Program Flash is always ON (default)
                        ; 1 = Program Flash is off in IDLE or Sleep mode
                        ; 2 - 3 = reserved
;
; CPSYS: Clock Prescaler for System (SYSCON1.8 .. SYSCON1.10)
_CPSYS    EQU    0      ; 0 = clock signal for CPU is PLL frequency
                        ; 1 = clock signal for CPU is PLL frequency / 2
                        ; 2 - 7 = reserved
;
;
; Definitions for System Configuration Register SYSCON3
; =====================================================
;
; INIT_SYSCON3: Init SYSCON3 register
; --- Set INIT_SYSCON3 = 1 to initilize the SYSCON3 register
$SET (INIT_SYSCON3 = 1)
;
; SYSCON3:  Power Management (disable on-chip peripherals)
;
ADCDIS  EQU     0       ; 1 = disable Analog/Digital Converter    (SYSCON3.0)
ASC0DIS EQU     0       ; 1 = disable UART ASC0                   (SYSCON3.1)
SSC0DIS EQU     0       ; 1 = disable Synchronus Serial Cnl0 SSC0 (SYSCON3.2)
GPTDIS  EQU     0       ; 1 = disable Timer Block GPT             (SYSCON3.3)
                        ; reserved                                (SYSCON3.4)
FMDIS   EQU     0       ; 1 = disable on-chip Flash Memory Module (SYSCON3.5)
CC1DIS  EQU     0       ; 1 = disable CAPCOM Unit 1               (SYSCON3.6)
CC2DIS  EQU     0       ; 1 = disable CAPCOM Unit 2               (SYSCON3.7)
CC6DIS  EQU     0       ; 1 = disable CAPCOM Unit 6               (SYSCON3.8)
                        ; reserved                                (SYSCON3.9)
ASC1DIS EQU     0       ; 1 = disable UART ASC1                   (SYSCON3.10)
I2CDIS  EQU     0       ; 1 = disable I2C Bus Module              (SYSCON3.11)
SDLMDIS EQU     0       ; 1 = disable SDLM (J1850) Module         (SYSCON3.12)
CANDIS  EQU     0       ; 1 = disable on-chip CAN Module          (SYSCON3.13)
                        ; reserved                                (SYSCON3.14)
SSC1DIS EQU     0       ; 1 = disable Synchronus Serial Cnl1 SSC1 (SYSCON3.15)
;
;
;
; Definitions for Reset Configuration Register RSTCON
; ===================================================
;
; INIT_RSTCON: Init RSTCON register
; --- Set INIT_RSTCON = 1 to initilize the RSTCON register
$SET (INIT_RSTCON = 0)
;
; RSTLEN: Reset Length Control (RSTCON.0 .. RSTCON.2)
_RSTLEN   EQU    0      ; 0 =   2 t_CPU clocks (default)
                        ; 1 =   4 t_CPU clocks
                        ; 2 =   8 t_CPU clocks
                        ; 3 =  16 t_CPU clocks
                        ; 4 =  32 t_CPU clocks
                        ; 5 =  64 t_CPU clocks
                        ; 6 = 128 t_CPU clocks
                        ; 7 = 256 t_CPU clocks
;
; RORMV: RSTOUT# Remove Control (RSTCON.4)
_RORMV    EQU    0      ; 0 = RSTOUT delievers RSTOUT# signal
                        ; 1 = RSTOUT pin operates as GPIO
;
; ROCOFF: RSTOUT# Control Switch Off (RSTCON.5)
_ROCOFF   EQU    0      ; 0 = RSTOUT is deactivated by user software
                        ; 1 = RSTOUT is deactiveted at end of reset
;
; ROCON: RSTOUT# Control Switch Off (RSTCON.6)
_ROCON    EQU    0      ; 0 = RSTOUT is activated upon any reset
                        ; 1 = RSTOUT is only activated upon a hardware reset
;
; RODIS: RSTOUT# Disable Control (RSTCON.7)
_RODIS    EQU    0      ; 0 = RSTOUT is controlled by other mechanism
                        ; 1 = RSTOUT is deactivated
;
;
;
; Definitions for PLL Control Register PLLCON
; ===========================================
;
; INIT_PLLCON: Init PLLCON register
; --- Set INIT_PLLCON = 1 to initilize the PLLCON register
$SET (INIT_PLLCON = 1)
;
; PLLODIV: PLL Output Devider (PLLCON.0 .. PLLCON.3)
_PLLODIV  EQU    9      ; 0 .. 14  Fpll = Fvco / (PLLODIV+1)
                        ; 15 = reserved
;
; PLLIDIV: PLL Input Devider (PLLCON.4 .. PLLCON.5)
_PLLIDIV  EQU    0      ; 0 .. 3   Fin = Fosc / (PLLIDIV+1)
;
; PLLVB: PLL VCO Band Select (PLLCON.6 .. PLLCON.7)
_PLLVB    EQU    2      ; ValueVCO output frequency    Base frequency
                        ; 0 = 100...150 MHz            20...80 MHz
                        ; 1 = 150...200 MHz            40...130 MHz
                        ; 2 = 200...250 MHz [def.]     60...180 MHz
                        ; 3 = (250...300 MHz) Reserved
;
; PLLMUL: PLL Multiplication Factor (PLLCON.8 .. PLLCON.12)
_PLLMUL   EQU    24     ; 7 .. 31  Fvco = Fin * (PLLMUL+1)
                        ; 0 .. 6 = reserved
;
; PLLCTRL: PLL Operation Control (PLLCON.13 .. PLLCON.14)
_PLLCTRL  EQU    3      ; 0 = Bypass PLL clock mult., the VCO is off
                        ; 1 = Bypass PLL clock mult., the VCO is running
                        ; 2 = VCO clock used, input clock switched off
                        ; 3 = VCO clock used, input clock connected
;
; PLLWRI: PLLCON Write Ignore Flag (PLLCON.15)
_PLLWRI   EQU    0      ; 0 = Register PLLCON may be written
                        ; 1 = Write cycles to register PLLCON are ignored
;
;
; Definitions for Watchdog Timer Control Register WDTCON
; ======================================================
;
; --- Set WATCHDOG = 1 to enable the Hardware watchdog and initilize the WDTCON register
$SET (WATCHDOG = 0)     ; 0 = Disabled Hardware watchdog
;
; WDTIN: Watchdog Timer Input Frequency Select (WDTCON.0 .. WDTCON.1)
_WDTIN    EQU    1      ; 0 = frequency f_peripheral / 2   (CPU default)  
                        ; 1 = frequency f_peripheral / 128 (recommended for START_V2)
                        ; 2 = frequency f_peripheral / 4
                        ; 3 = frequency f_peripheral / 256
;
; WDTREL: Watchdog Timer Reload Value (WDTCON8 .. WDTCON15)
_WDTREL   EQU    0      ; high byte of WDT (counts up, overflow gives Watchdog reset)
;
;
; Definitions for Frequency Output Signal FOCON
; =============================================
;
; INIT_FOCON: Init FOCON register
; --- Set INIT_FOCON = 1 to initilize the FOCON register
$SET (INIT_FOCON = 1)
;
; CLKEN: CLKOUT Enable (FOCON.7)
_CLKEN    EQU     0     ; 0 = P3.15 is IO pin when _FOUT is 0
                        ; 1 = P3.15 outputs signal CLKOUT
;