xrompower.c

GM5621原代码

    while(((gm_ReadRegByte (LOW_BW_ADC_STATUS)) & BIT0)==0)	continue;

    #if	AdcPolarity
        B_Key = ~((BYTE) gm_ReadRegByte (LOW_BW_ADC_RESULT));	// Read key data
    #else
        B_Key = (BYTE) gm_ReadRegByte (LOW_BW_ADC_RESULT);	// Read key data
    #endif

	//
	// Reset the Low Bandwidth ADC control register to idle.
	//
	gm_WriteRegByte (LOW_BW_ADC_CTRL, B_Ctrl);

	return B_Key;
}
#endif //LBADC_USED

//*************************************************************************
// FUNCTION     : ScanADCKeyRAM
// USAGE        : ScanADCKeyRAM(void)
// DESCRIPTION  : This function scans all channels of the low bandwidth ADC.
// 					If any key is pressed it returns gmd_TRUE. Otherwise, it
// 					returns gmd_FALSE.
// INPUT        : None
// OUTPUT       : None
// GLOBALS      : None
// USED_REGS    : None
//*************************************************************************
#if LBADC_USED
static __near BYTE ScanADCKeyRAM( void )
{
	BYTE B_ADCKey = 0;

	#ifdef PORT_ADC_1_USED
		B_ADCKey = ScanADCKeyOnChannelRAM( LBADC_IN1);
	#endif

	#ifdef PORT_ADC_2_USED
		B_ADCKey = ScanADCKeyOnChannelRAM( LBADC_IN2);
	#endif

	#ifdef PORT_ADC_3_USED
		B_ADCKey = ScanADCKeyOnChannelRAM( LBADC_IN3);
	#endif

	if ( B_ADCKey > XROM_LBADC_NOISE_THRESHOLD )
	{
		msg("RAM - ADC scan code: 0x%x", B_ADCKey);
		return( gmd_TRUE );
	}

	return( gmd_FALSE );
}
#endif // LBADC_USED

//*************************************************************************
// FUNCTION     : ReadKeypadRAM
// USAGE        : ReadKeypadRAM(void)
// DESCRIPTION  : This function is a wrapper for scanning key presses on
// 					GPIO or low bandwidth ADC.
// INPUT        : None
// OUTPUT       : None
// GLOBALS      : None
// USED_REGS    : None
//*************************************************************************
static __near BYTE ReadKeypadRAM( void )
{
	BYTE retVal1 = gmd_FALSE;
	BYTE retVal2 = gmd_FALSE;

#if USE_GPIO_KEYPAD
	retVal1 = ReadGPIOKeypadRAM();
#endif

#if LBADC_USED
	retVal2 = ScanADCKeyRAM();
#endif

	return ( retVal1 | retVal2 );
}

//*************************************************************************
// FUNCTION     : SerialHandlerRAM
// USAGE        : SerialHandlerRAM()
// DESCRIPTION  : This function directly calls the IROM serial handler
// INPUT        : None
// OUTPUT       : None
// GLOBALS      : None
// USED_REGS    : None
//*************************************************************************
static __near SerialMsgStatus_t SerialHandlerRAM( void )
{
	return( gmi_SystemDebug() );
}


//*************************************************************************
// FUNCTION     : CommonInterruptHandlerRAM. Interrupt Service Routine.
// USAGE        : It is typically not called directly. Set up as a vector.
// DESCRIPTION  : This function is the interrupt service routine common to
//              : certain interrupts.
// INPUT        : None
// OUTPUT       : None
// GLOBALS      : None
// USED_REGS    : None
// Note: This function is executed in interrupt context.
//*************************************************************************
void interrupt CommonInterruptHandlerRAM( void )
{
	// A common interrupt handler for exceptions caused
	// due to system anamolies, like divide by zero, bounds,
	// unused opcode, etc. This interrupt handler needs to be
	// in RAM.
}


//*************************************************************************
// FUNCTION     : NMIHandlerRAM. Interrupt Service Routine.
// USAGE        : It is typically not called directly. Set up as a vector.
// DESCRIPTION  : This function is the interrupt service routine for the
//              : non-maskable interrupt.
// INPUT        : None
// OUTPUT       : None
// GLOBALS      : None
// USED_REGS    : None
// Note: This function is executed in interrupt context.
//*************************************************************************
void interrupt NMIHandlerRAM( void )
{
#if  UseWatchdogTimer == 1
		#if RESET_ON_WDT
			ResetOCMRAM();
		#endif
#endif // UseWatchdogTimer
}

#ifdef PORT_IR_USED
//******************************************************************************
//
// FUNCTION:    interrupt IRStartInterrupt(void)
// USAGE:       Rising edge interrupt service routine
//
// INPUT:       None
// OUTPUT:      None
// GLOBALS:		None
// USED_REGS:	T1CNT, T1CON, IMASK, EOI
//******************************************************************************
#if IR_DRIVER != USE_RC5
void interrupt IREdgeInterruptRAM(void)
{
	if(B_IrClockCounterRAM > IR_LEADER)
    {
		IrIndexRAM = 0;
        IrLWordRAM = 0;
	    #if USE_HT6222_RC 
        	W_IrPacketCounterRAM = 0;
        #endif
    }
    else
    {
    	#if IR_REPEAT
		if(B_IrClockCounterRAM > IR_REPEAT)
        {
	        W_IrPacketCounterRAM = 0;
        }
        else
        #endif
    		IrIndexRAM++;
    }

    #if USE_HT6222_RC == 0
        W_IrPacketCounterRAM = 0;
    #endif

    if( (B_IrClockCounterRAM < IR_LOGIC0_MAX) && (B_IrClockCounterRAM > IR_LOGIC0_MIN))
    {
    	IrLWordRAM <<= 1;
    } 

    if( (B_IrClockCounterRAM < IR_LOGIC1_MAX) && (B_IrClockCounterRAM > IR_LOGIC1_MIN))
    {
        IrLWordRAM <<= 1;
        IrLWordRAM |= 0x0001;
    }

	#if IR_DEVICE_LENGTH
    if(IrIndexRAM == IR_DEVICE_LENGTH)
    {
    	IrAddressRAM = IrLWordRAM;
    }
    #endif
    
    if(IrIndexRAM == IR_DATA_LENGTH)
    {
    	IRKey = IrLWordRAM;
    	IrIndexRAM = 0;
    	IrLWordRAM = 0;
    }

    if(IrIndexRAM > IR_DATA_LENGTH)
	 {
	 	IrIndexRAM = 0;
		IrLWordRAM = 0;
	 }


    WRITE_PCB_REG(T1CNT, 0);                    // Clear counter
    WRITE_PCB_REG(T1CON, (EN|INH|INT|CONT));		// Enable timer interrupt
    CLEAR_PCB_REG_BITS(IMASK, TMR);

    B_IrClockCounterRAM = 0;
	WRITE_PCB_REG(EOI, INT2_VTYPE);			// Clear interrupt
}


//***********************************************************************
// FUNCTION    : IRTimerIntRAM 
// USAGE       : It is typically not called directly. Set up as a vector.
// DESCRIPTION : This function is the interrupt service routine for the
//               IR interrupt timer. Timer 2 is used as the IR interrupt
//               timer.
//
// INPUTS      : none
// OUTPUTS     : none
// RETURNS	   : none
// GLOBALS     : B_IrClockCounterRAM, W_IrPacketCounterRAM, IRKey 
// USED_REGS   : TICON, EOI
// Note: This function is executed in interrupt context.
//***********************************************************************
void far interrupt IRTimerIntRAM(void)
{ 
	B_IrClockCounterRAM++;
	W_IrPacketCounterRAM++;
	if(W_IrPacketCounterRAM > IR_AUTOREPEAT_RESET)
	{
		// Clear key
		IRKey = 0;
		// disable timer interrupt
		WRITE_PCB_REG(T1CON, (INH|INT|CONT));
		B_IrClockCounterRAM = 0;
		W_IrPacketCounterRAM = 0;
	}

	IRInterruptOccurred = gmd_TRUE;		// Set flag to tell RAM loop IR interrupt occurred

	CLEAR_PCB_REG_BITS(T1CON, MC);
	WRITE_PCB_REG(EOI, TIMER1_VTYPE);
}

#else	// RC5

void interrupt IREdgeInterruptRAM(void)
{
    IrIndexRAM = 0;
    IrLWordRAM = 0;
    B_EdgeStateRAM = 0;
    W_IrPacketCounterRAM = 0;

	WRITE_PCB_REG(T1CNT, 0);		// Clear counter value
    WRITE_PCB_REG(T1CMPA, W_IRPeriodTImeRAM + (W_IRPeriodTImeRAM >> 1));   // Configure timer1 value

    WRITE_PCB_REG(T1CON, (EN|INH|INT|CONT));	// Enable timer interrupt
    CLEAR_PCB_REG_BITS(IMASK, TMR);
    
	SET_PCB_REG_BITS(IMASK, I2);	// Mask this interrupt
    gm_ClearRegBitsWord(IRQ_CONFIG, GPIO_IRQ_IN_EN);	// enable GPIO input
        
	WRITE_PCB_REG(EOI, INT2_VTYPE);			// Clear interrupt
}

void far interrupt IRTimerIntRAM(void)
{
	BYTE B_Input;
    WRITE_PCB_REG(T1CMPA, W_IRPeriodTImeRAM);   // Configure timer1 value

        
    B_Input = gm_ReadRegWord(GPINPUT1) & INPUT_BIT_MASK;
    if(IrIndexRAM == 0)
        B_EdgeStateRAM = B_Input;

    if(IrIndexRAM < IR_DATA_LENGTH)
    {
        if(IrIndexRAM & 0x01)
        {
            if(B_EdgeStateRAM != B_Input)
            {
                IrLWordRAM <<= 1;
                if(B_Input)
                    IrLWordRAM |= 0x0001;
            }
        }
        IrIndexRAM++;
        B_EdgeStateRAM = B_Input;
    }
    else
    {
        if(IrLWordRAM & 0x1000)
        {
        	if((IrLWordRAM & 0x07ff) == 0)
            	IrLWordRAM = ZERRO_KEY_CODE;
            IRKey = IrLWordRAM & 0x07ff;
	        W_IrPacketCounterRAM = IR_DATA_LENGTH  + 1;
        }
        IrLWordRAM = 0;
        IrIndexRAM = 0;
        gm_SetRegBitsWord(IRQ_CONFIG, GPIO_IRQ_IN_EN);	// enable GPIO input
        CLEAR_PCB_REG_BITS(IMASK, I2);	// Mask this interrupt
    }

    W_IrPacketCounterRAM++;
    if(W_IrPacketCounterRAM > IR_AUTOREPEAT_RESET)
    {
        IRKey = 0;
        IrLWordRAM = 0;
        IrIndexRAM = 0;
        // disable timer interrupt
        WRITE_PCB_REG(T1CON, (INH|INT|CONT));
        SET_PCB_REG_BITS(IMASK, TMR);
    }

	 IRInterruptOccurred = gmd_TRUE;	// Set flag to indicate IR interrupt occurred
	 
	CLEAR_PCB_REG_BITS(T1CON, MC);
	WRITE_PCB_REG(EOI, TIMER1_VTYPE);
}
#endif	// RC5
#endif // PORT_IR_USED


#if (ProcessExceptions != DisableExceptions) && (UseWatchdogTimer == 1)
//***********************************************************************
// FUNCTION    : PetWatchdogRAM
// USAGE       : PetWatchdogRAM()
// DESCRIPTION : This function resets the software watchdog counter.
//               The counter is checked in the watchdog interrupt
//               handler.
//
// INPUTS      : none
// OUTPUTS     : none
// RETURNS	   : none
// GLOBALS     : watchdog
// USED_REGS   : none directly
//***********************************************************************
static __near void PetWatchdogRAM(void)
{
// Reset the H/W watchdog counter 
	WRITE_PCB_REG(WDTCON,0xAAAA);
	WRITE_PCB_REG(WDTCON,0x5555);
}
#endif // (ProcessExceptions != DisableExceptions) && (UseWatchdogTimer == 1)


#if RESET_ON_WDT
//***********************************************************************
// FUNCTION    : ResetOCMRAM 
// USAGE       : ResetOCMRAM()
// DESCRIPTION : This function resets the gm5221 chip registers,
//               and finally the OCM itself. This function is called
//               if an NMI is generated by the watchdog timer.
//
// INPUTS      : none
// OUTPUTS     : none
// RETURNS	   : none
// GLOBALS     : watchdog
// USED_REGS   : HOST_CONTROL, CLOCK_CONFIG 
// NOTE			: This function runs in the interrupt context.
//***********************************************************************
static __near void ResetOCMRAM(void)
{
	// Soft reset 52xx registers
	EnableXROMPower();
	gm_WriteRegByte(HOST_CONTROL,SOFT_RESET);
	// software delay calibrated to be 1ms at 100Mhz OCM speed running out
	// of RAM.  When running from parallel flash you can expect the delay
	// to be about 2.5 times longer (2.5ms)
	for(i=0;i<0x500;i++)
		val ^= i;
	// Disable all interrupts 
	gm_DisableInterrupts();
	gm_WriteRegByte(CLOCK_CONFIG,0x42);
	gm_WriteRegByte(OCM_CONTROL,OCM_RESET); // note, OCM_RESET is self clearing
}
#endif


//***********************************************************************
// FUNCTION     : DummyFunc2GetCodeSize
// USAGE        :	DummyFunc2GetCodeSize()
// DESCRIPTION  :	This is a dummy function which serves as the end
//						of the code block that need to move to RAM for
//						execution during deep sleep mode. The body of
//						the function is not copied to RAM.
//
// INPUTS       :	none
// OUTPUTS      :	none
// RETURNS      :	none
// GLOBALS      :	none
// USED_REGS    :	none
// NOTE         : This must be the last function in the code block
//                that is copied to RAM.
//***********************************************************************
void DummyFunc2GetCodeSize(void)
{

}

#endif // USE_POWERDOWN_ROM_CE