appstest.c

GM5621原代码

	//{DVI_SIGQUAL_1,					0xff},	   //141 (IP_HI)
	//{DVI_SIGQUAL_2,					0xff},	   //142 (IP_LO)
	//{DVI_PHASE_A_SCORE_0,			0xff},	   //144 (IP_LO)
	//{DVI_PHASE_A_SCORE_1,			0xff},	   //145 (IP_HI)
	//{DVI_PHASE_A_SCORE_2,			0xff},	   //146 (IP_LO)
	//{DVI_PHASE_B_SCORE_0,			0xff},	   //148 (IP_LO)
	//{DVI_PHASE_B_SCORE1,			0xff},	   //149 (IP_HI)
	//{DVI_PHASE_B_SCORE_2,			0xff},	   //150 (IP_LO)
	//{DVI_PHASE_C_SCORE_0,			0xff},	   //152 (IP_LO)
	//{DVI_PHASE_C_SCORE_1,			0xff},	   //153 (IP_HI)
	//{DVI_PHASE_C_SCORE_2,			0xff},	   //154 (IP_LO)
	//{DVI_RCAL_RESULT_0,			0xf },	   //156 (IP_LO)
	//{DVI_RCAL_RESULT_1         	0xFF}
	//{DVI_RCAL_RESULT_2         	0xFF}
	{IP_CONTROL,						0xf7},	   //160 (IP_LO)
	{IP_POLARITY,						0x1f},	   //161 (IP_HI)
	{CSYNC_CONTROL,					0xff},	   //163 (IP_HI)
	{COAST_START_0,					0xff},	   //164 (IP_LO)
	{COAST_START_1,					0x7 },	   //165 (IP_HI)
	{COAST_END_0,						0xff},	   //166 (IP_LO)
	{COAST_END_1,						0x7 },	   //167 (IP_HI)
	{IPHS_DELAY_0,						0xff},	   //168 (IP_LO)
	{IPHS_DELAY_1,						0xf },	   //169 (IP_HI)
	{IPVS_DELAY_0,						0xff},	   //170 (IP_LO)
	{IPVS_DELAY_1,						0x7 },	   //171 (IP_HI)
	{IPH_ACT_START_0,					0xff},	   //172 (IP_LO)
	{IPH_ACT_START_1,					0xf },	   //173 (IP_HI)
	{IPH_ACT_WIDTH_0,					0xff},	   //174 (IP_LO)
	{IPH_ACT_WIDTH_1,					0xf },	   //175 (IP_HI)
	{IPV_ACT_START_ODD_0,			0xff},	   //176 (IP_LO)
	{IPV_ACT_START_ODD_1,			0x7 },	   //177 (IP_HI)
	{IPV_ACT_START_EVEN_0,			0xff},	   //178 (IP_LO)
	{IPV_ACT_START_EVEN_1,			0x7 },	   //179 (IP_HI)
	{IPV_ACT_LENGTH_0,				0xff},	   //180 (IP_LO)
	{IPV_ACT_LENGTH_1,				0x7 },	   //181 (IP_HI)
	{SRC_VTOTAL_0,						0xff},	   //182 (IP_LO)
	{SRC_VTOTAL_1,						0x7 },	   //183 (IP_HI)
	{IP_FLAGLINE_0,					0xff},	   //184 (IP_LO)
	{IP_FLAGLINE_1,					0x7 },	   //185 (IP_HI)
	{PATGEN_CONTROL,					0xff},	   //192 (IP_LO)
	{PATGEN_BLUE,						0xff},	   //193 (IP_HI)
	{PATGEN_GRN,						0xff},	   //194 (IP_LO)
	{PATGEN_RED,						0xff},	   //195 (IP_HI)
	{PATGEN_H_PITCH,					0xff},	   //196 (IP_LO)
	{PATGEN_V_PITCH,					0xff},	   //197 (IP_HI)
	{PATGEN_H_INC_R,					0xff},	   //198 (IP_LO)
	{PATGEN_V_INC_R,					0xff},	   //199 (IP_HI)
	{PATGEN_H_INC_G,					0xff},	   //200 (IP_LO)
	{PATGEN_V_INC_G,					0xff},	   //201 (IP_HI)
	{PATGEN_H_INC_B,					0xff},	   //202 (IP_LO)
	{PATGEN_V_INC_B,					0xff},	   //203 (IP_HI)
	{IFM_CTRL,							0xbf},	   //206 (IFM_LO)
	{IFM_WATCHDOG,						0xff},	   //207 (IFM_HI)
	{IFM_FIELD_CONTROL,				0xff},	   //208 (IFM_LO)
	{IFM_CHANGE,						0xff},	   //209 (IFM_HI)
	{IFM_HLINE_0,						0xff},	   //210 (IFM_LO)
	{IFM_HLINE_1,						0xf },	   //211 (IFM_HI)
	//{IFM_HS_PERIOD_0,				0xff},	   //212 (IFM_LO)
	//{IFM_HS_PERIOD_1,				0xf },	   //213 (IFM_HI)
	//{IFM_HS_PULSE_0,				0xff},	   //214 (IFM_LO)
	//{IFM_HS_PULSE_1,				0xf },	   //215 (IFM_HI)
	//{IFM_VS_PERIOD_0,				0xff},	   //216 (IFM_LO)
	//{IFM_VS_PERIOD_1,				0xf },	   //217 (IFM_HI)
	//{IFM_VS_PULSE_0,				0xff},	   //218 (IFM_LO)
	//{IFM_VS_PULSE_1,				0xf },	   //219 (IFM_HI)
	//{IFM_CSYNC_SPACE,				0xf },	   //220 (IFM_LO)
	//{IBD_CONTROL,					0xff},	   //223 (IP_HI)
	//{IBD_VSTART_0,					0xff},	   //224 (IP_LO)
	//{IBD_VSTART_1,					0x7 },	   //225 (IP_HI)
	//{IBD_VLENGTH_0,					0xff},	   //226 (IP_LO)
	//{IBD_VLENGTH_1,					0x7 },	   //227 (IP_HI)
	//{IBD_HSTART_0,					0xff},	   //228 (IP_LO)
	//{IBD_HSTART_1,					0xf },	   //229 (IP_HI)
	//{IBD_HWIDTH_0,					0xff},	   //230 (IP_LO)
	//{IBD_HWIDTH_1,					0xf },	   //231 (IP_HI)
	//{IBD_HTOTAL_0,					0xff},	   //232 (IP_LO)
	//{IBD_HTOTAL_1,					0xf },	   //233 (IP_HI)
	//{IBD_VTOTAL_0,					0xff},	   //234 (IP_LO)
	//{IBD_VTOTAL_1,					0x7 },	   //235 (IP_HI)
	{PIXGRAB_X_0,						0xff},	   //236 (IP_LO)
	{PIXGRAB_X_1,						0x1f},	   //237 (IP_HI)
	{PIXGRAB_Y_0,						0xff},	   //238 (IP_LO)
	{PIXGRAB_Y_1,						0x7 },	   //239 (IP_HI)
	//{PIXGRAB_RED,					0xff},	   //240 (IP_LO)
	//{PIXGRAB_GRN,					0xff},	   //241 (IP_HI)
	//{PIXGRAB_BLU,					0xff},	   //242 (IP_LO)
	{INST_AUTO_CTRL,					0x7f},	   //248 (IP_LO)
	{INST_AUTO_EDGE_THRESH,			0xff},	   //249 (IP_HI)
	{INST_AUTO_LEVEL_THRESH,		0xff},	   //250 (IP_LO)
	#ifdef SUMDIFF_MINMAX
	{SUMDIFF_MINMAX,					0x1f},	   //258 (IP_LO)
	{SDIFF_THRESHOLD,					0xff},	   //259 (IP_HI)
	//{SDIFF_RESULT_0,				0xff},	   //260 (IP_LO)
	//{SDIFF_RESULT_1,				0xff},	   //261 (IP_HI)
	//{SDIFF_RESULT_2,				0xff},	   //262 (IP_LO)
	//{SDIFF_RESULT_3,				0xff},	   //263 (IP_HI)
	//{MINMAX_BLUE,					0xff},	   //264 (IP_LO)
	//{MINMAX_GREEN,					0xff},	   //265 (IP_HI)
	//{MINMAX_RED,						0xff},	   //266 (IP_LO)
	#endif //SUMDIFF_MINMAX
   #if !defined(TUCSON)
	{CLKMEAS_CONTROL,					0x1f},	   //268 (IP_LO)
	{CLKMEAS_THRESH,					0x3f},	   //269 (IP_HI)
   #endif
	//{CLKMEAS_RESULT_0,				0xff},	   //270 (IP_LO)
	//{CLKMEAS_RESULT_1,				0xf },	   //271 (IP_HI)
	{FILTER_CONTROL,					0xcf},	   //272 (EXP_LO)
	{FILTER_COEFF_INDEX,				0x3f},	   //273 (EXP_HI)
	//{FILTER_COEFF,					0x3f},	   //274 (EXP_LO)
   #ifndef PHOENIX_U
	{FILTER_DITHER_CTRL,				0xf },	   //275 (EXP_HI)
   #endif
	{VF_START_OFFSET_0,				0xff},	   //276 (EXP_LO)
	{VF_START_OFFSET_1,				0x1f},	   //277 (EXP_HI)
	{Z_HORZ_SV_0,						0xff},	   //278 (EXP_LO)
	{Z_HORZ_SV_1,						0xff},	   //279 (EXP_HI)
	{Z_HORZ_SV_2,						0xf },	   //280 (EXP_LO)
	{Z_VERT_SV_0,						0xff},	   //282 (EXP_LO)
	{Z_VERT_SV_1,						0xff},	   //283 (EXP_HI)
	{Z_VERT_SV_2,						0xf },	   //284 (EXP_LO)
	{HOR_INIT_PHASE,					0x1f},	   //286 (EXP_LO)
	{VERT_INIT_PHASE,					0x1f},	   //287 (EXP_HI)
	{HOR_ALT_PHASE,					0x1f},	   //288 (EXP_LO)
	{VERT_ALT_PHASE,					0x1f},	   //289 (EXP_HI)
	{OSD_ENABLES,						0x13},	   //296 (OSD_LO)
	{OSD_CONTROL,						0x13},	   //297 (OSD_HI)
	{OSD_BLINK_ON,						0x3f},	   //298 (OSD_LO)
	{OSD_BLINK_OFF,					0x3f},	   //299 (OSD_HI)
	{OSD_BLEND_TABLE0,				0xff},	   //300 (OSD_LO)
	{OSD_BLEND_TABLE1,				0xff},	   //301 (OSD_HI)
	{OSD_BLEND_TABLE2,				0xff},	   //302 (OSD_LO)
	{OSD_BLEND_TABLE3,				0xff},	   //303 (OSD_HI)
	{OSD_R1_HSTART_0,					0xff},	   //304 (OSD_LO)
	{OSD_R1_HSTART_1,					0xf },	   //305 (OSD_HI)
	{OSD_R1_VSTART_0,					0xff},	   //306 (OSD_LO)
	{OSD_R1_VSTART_1,					0x7 },	   //307 (OSD_HI)
	{OSD_R1_WIDTH_0,					0xff},	   //308 (OSD_LO)
	{OSD_R1_WIDTH_1,					0xf },	   //309 (OSD_HI)
	{OSD_R1_HEIGHT_0,					0xff},	   //310 (OSD_LO)
	{OSD_R1_HEIGHT_1,					0x7 },	   //311 (OSD_HI)
	{OSD_R1_YSTRIDE,					0xff},	   //312 (OSD_LO)
	{OSD_R1_FONT_SIZE,				0xf7},	   //313 (OSD_HI)
	{OSD_R1_CHARMAP_CTRL,			0xdf},	   //314 (OSD_LO)
	{OSD_R1_WIN_EN,					0xf },	   //315 (OSD_HI)
	{OSD_R1_WIN_INDEX0,				0xff},	   //316 (OSD_LO)
	{OSD_R1_WIN_INDEX1,				0xff},	   //317 (OSD_HI)
	{OSD_R1_W1_HSTART_0,				0xff},	   //318 (OSD_LO)
	{OSD_R1_W1_HSTART_1,				0xf },	   //319 (OSD_HI)
	{OSD_R1_W1_VSTART_0,				0xff},	   //320 (OSD_LO)
	{OSD_R1_W1_VSTART_1,				0x7 },	   //321 (OSD_HI)
	{OSD_R1_W1_HEND_0,				0xff},	   //322 (OSD_LO)
	{OSD_R1_W1_HEND_1,				0xf },	   //323 (OSD_HI)
	{OSD_R1_W1_VEND_0,				0xff},	   //324 (OSD_LO)
	{OSD_R1_W1_VEND_1,				0x7 },	   //325 (OSD_HI)
	{OSD_R1_W2_HSTART_0,				0xff},	   //326 (OSD_LO)
	{OSD_R1_W2_HSTART_1,				0xf },	   //327 (OSD_HI)
	{OSD_R1_W2_VSTART_0,				0xff},	   //328 (OSD_LO)
	{OSD_R1_W2_VSTART_1,				0x7 },	   //329 (OSD_HI)
	{OSD_R1_W2_HEND_0,				0xff},	   //330 (OSD_LO)
	{OSD_R1_W2_HEND_1,				0xf },	   //331 (OSD_HI)
	{OSD_R1_W2_VEND_0,				0xff},	   //332 (OSD_LO)
	{OSD_R1_W2_VEND_1,				0x7 },	   //333 (OSD_HI)
	{OSD_R1_W3_HSTART_0,				0xff},	   //334 (OSD_LO)
	{OSD_R1_W3_HSTART_1,				0xf },	   //335 (OSD_HI)
	{OSD_R1_W3_VSTART_0,				0xff},	   //336 (OSD_LO)
	{OSD_R1_W3_VSTART_1,				0x7 },	   //337 (OSD_HI)
	{OSD_R1_W3_HEND_0,				0xff},	   //338 (OSD_LO)
	{OSD_R1_W3_HEND_1,				0xf },	   //339 (OSD_HI)
	{OSD_R1_W3_VEND_0,				0xff},	   //340 (OSD_LO)
	{OSD_R1_W3_VEND_1,				0x7 },	   //341 (OSD_HI)
	{OSD_R1_W4_HSTART_0,				0xff},	   //342 (OSD_LO)
	{OSD_R1_W4_HSTART_1,				0xf },	   //343 (OSD_HI)
	{OSD_R1_W4_VSTART_0,				0xff},	   //344 (OSD_LO)
	{OSD_R1_W4_VSTART_1,				0x7 },	   //345 (OSD_HI)
	{OSD_R1_W4_HEND_0,				0xff},	   //346 (OSD_LO)
	{OSD_R1_W4_HEND_1,				0xf },	   //347 (OSD_HI)
	{OSD_R1_W4_VEND_0,				0xff},	   //348 (OSD_LO)
	{OSD_R1_W4_VEND_1,				0x7 },	   //349 (OSD_HI)
	{OSD_R1_1BIT_FONT_BA_0,			0xff},	   //350 (OSD_LO)
	{OSD_R1_1BIT_FONT_BA_1,			0x3f},	   //351 (OSD_HI)
	{OSD_R1_X1BIT_FONT_BA_0,		0xff},	   //352 (OSD_LO)
	{OSD_R1_X1BIT_FONT_BA_1,		0x3f},	   //353 (OSD_HI)
	{OSD_R1_2BIT_FONT_BA_0,			0xff},	   //354 (OSD_LO)
	{OSD_R1_2BIT_FONT_BA_1,			0x3f},	   //355 (OSD_HI)
	{OSD_R1_4BIT_FONT_BA_0,			0xff},	   //356 (OSD_LO)
	{OSD_R1_4BIT_FONT_BA_1,			0x3f},	   //357 (OSD_HI)
	{OSD_R1_ATTR_BA_0,				0xff},	   //358 (OSD_LO)
	{OSD_R1_ATTR_BA_1,				0x3f},	   //359 (OSD_HI)
	{OSD_R1_CCF_BA_0,					0xff},	   //360 (OSD_LO)
	{OSD_R1_CCF_BA_1,					0x3f},	   //361 (OSD_HI)
	{OSD_R2_HSTART_0,					0xff},	   //362 (OSD_LO)
	{OSD_R2_HSTART_1,					0xf },	   //363 (OSD_HI)
	{OSD_R2_VSTART_0,					0xff },	   //364 (OSD_LO)
	{OSD_R2_VSTART_1,					0x7 },	   //365 (OSD_HI)
	{OSD_R2_WIDTH_0,					0xff},	   //366 (OSD_LO)
	{OSD_R2_WIDTH_1,					0xf },	   //367 (OSD_HI)
	{OSD_R2_HEIGHT_0,					0xff},	   //368 (OSD_LO)
	{OSD_R2_HEIGHT_1,					0x7 },	   //369 (OSD_HI)
	{OSD_R2_YSTRIDE,					0xff},	   //370 (OSD_LO)
	{OSD_R2_FONT_SIZE,				0xf7},	   //371 (OSD_HI)
	{OSD_R2_CHARMAP_CTRL,			0xdf},	   //372 (OSD_LO)
	{OSD_R2_WIN_EN,					0xf },	   //373 (OSD_HI)
	{OSD_R2_WIN_INDEX0,				0xff},	   //374 (OSD_LO)
	{OSD_R2_WIN_INDEX1,				0xff},	   //375 (OSD_HI)
	{OSD_R2_W1_HSTART_0,				0xff},	   //376 (OSD_LO)
	{OSD_R2_W1_HSTART_1,				0xf },	   //377 (OSD_HI)
	{OSD_R2_W1_VSTART_0,				0xff},	   //378 (OSD_LO)
	{OSD_R2_W1_VSTART_1,				0x7 },	   //379 (OSD_HI)
	{OSD_R2_W1_HEND_0,				0xff},	   //380 (OSD_LO)
	{OSD_R2_W1_HEND_1,				0xf },	   //381 (OSD_HI)
	{OSD_R2_W1_VEND_0,				0xff},	   //382 (OSD_LO)
	{OSD_R2_W1_VEND_1,				0x7 },	   //383 (OSD_HI)
	{OSD_R2_W2_HSTART_0,				0xff},	   //384 (OSD_LO)
	{OSD_R2_W2_HSTART_1,				0xf },	   //385 (OSD_HI)
	{OSD_R2_W2_VSTART_0,				0xff},	   //386 (OSD_LO)
	{OSD_R2_W2_VSTART_1,				0x7 },	   //387 (OSD_HI)
	{OSD_R2_W2_HEND_0,				0xff},	   //388 (OSD_LO)
	{OSD_R2_W2_HEND_1,				0xf },	   //389 (OSD_HI)
	{OSD_R2_W2_VEND_0,				0xff},	   //390 (OSD_LO)
	{OSD_R2_W2_VEND_1,				0x7 },	   //391 (OSD_HI)
	{OSD_R2_W3_HSTART_0,				0xff},	   //392 (OSD_LO)
	{OSD_R2_W3_HSTART_1,				0xf },	   //393 (OSD_HI)
	{OSD_R2_W3_VSTART_0,				0xff},	   //394 (OSD_LO)
	{OSD_R2_W3_VSTART_1,				0x7 },	   //395 (OSD_HI)
	{OSD_R2_W3_HEND_0,				0xff},	   //396 (OSD_LO)
	{OSD_R2_W3_HEND_1,				0xf },	   //397 (OSD_HI)
	{OSD_R2_W3_VEND_0,				0xff},	   //398 (OSD_LO)
	{OSD_R2_W3_VEND_1,				0x7 },	   //399 (OSD_HI)
	{OSD_R2_W4_HSTART_0,				0xff},	   //400 (OSD_LO)
	{OSD_R2_W4_HSTART_1,				0xf },	   //401 (OSD_HI)
	{OSD_R2_W4_VSTART_0,				0xff},	   //402 (OSD_LO)
	{OSD_R2_W4_VSTART_1,				0x7 },	   //403 (OSD_HI)
	{OSD_R2_W4_HEND_0,				0xff},	   //404 (OSD_LO)
	{OSD_R2_W4_HEND_1,				0xf },	   //405 (OSD_HI)
	{OSD_R2_W4_VEND_0,				0xff},	   //406 (OSD_LO)
	{OSD_R2_W4_VEND_1,				0x7 },	   //407 (OSD_HI)
	{OSD_R2_1BIT_FONT_BA_0,			0xff},	   //408 (OSD_LO)
	{OSD_R2_1BIT_FONT_BA_1,			0x3f},	   //409 (OSD_HI)
	{OSD_R2_X1BIT_FONT_BA_0,		0xff},	   //410 (OSD_LO)
	{OSD_R2_X1BIT_FONT_BA_1,		0x3f},	   //411 (OSD_HI)
	{OSD_R2_2BIT_FONT_BA_0,			0xff},	   //412 (OSD_LO)
	{OSD_R2_2BIT_FONT_BA_1,			0x3f},	   //413 (OSD_HI)
	{OSD_R2_4BIT_FONT_BA_0,			0xff},	   //414 (OSD_LO)
	{OSD_R2_4BIT_FONT_BA_1,			0x3f},	   //415 (OSD_HI)
	{OSD_R2_ATTR_BA_0,				0xff},	   //416 (OSD_LO)
	{OSD_R2_ATTR_BA_1,				0x3f},	   //417 (OSD_HI)
	{OSD_R2_CCF_BA_0,					0xff},	   //418 (OSD_LO)
	{OSD_R2_CCF_BA_1,					0x3f},	   //419 (OSD_HI)
	//{DDS_CONTROL,					0x7f},	   //416 (DDS_LO)
	//{DDS_STATUS,						0x3 },	   //417 (DDS_HI)
	//{SDDS_CONTROL,					0xff},	   //418 (DDS_LO)
	//{SDDS_INIT,						0x3f},	   //419 (HOST_HI)
	//{SDDS_INITIAL_FREQ_0,			0xff},	   //420 (DDS_LO)
	//{SDDS_INITIAL_FREQ_1,			0xff},	   //421 (DDS_HI)
	//{SDDS_INITIAL_FREQ_2,			0xff},	   //422 (DDS_LO)
	{SDDS_HTOTAL_0,					0xff},	   //424 (DDS_LO)
	{SDDS_HTOTAL_1,					0xf },	   //425 (DDS_HI)
	{SAMPLING_PHASE_DELAY,			0x3f},	   //426 (DDS_LO)
	//{SDDS_STEP_VAL,					0xff},	   //427 (DDS_HI)
	{SDDS_FREQUENCY_DELTA_THRESH,	0xff},	   //428 (DDS_LO)
	//{SDDS_TRACKING_ERR,			0xff},	   //429 (DDS_HI)
	//{SDDS_FREQUENCY_0,				0xff},	   //430 (DDS_LO)
	//{SDDS_FREQUENCY_1,				0xff},	   //431 (DDS_HI)
	//{SDDS_FREQUENCY_2,				0xff},	   //432 (DDS_LO)
	{SDDS_TEST_CNTRL0,				0xf },	   //434 (DDS_LO)
	{SDDS_TEST_CNTRL1,				0xff},	   //435 (DDS_HI)
	//{SDDS_TEST_DATA_0,				0xff},	   //438 (DDS_LO)
	//{SDDS_TEST_DATA_1,				0xff},	   //439 (DDS_HI)
	//{SDDS_TEST_DATA_2,				0xff},	   //440 (DDS_LO)
	//{DDDS_CONTROL,					0xfe},	   //442 (DDS_LO)
	//{DDDS_INIT,						0x1 },	   //443 (HOST_HI)
	//{DDDS_INITIAL_FREQUENCY_0,	0xff},	   //444 (DDS_LO)
	//{DDDS_INITIAL_FREQUENCY_1,	0xff},	   //445 (DDS_HI)
	//{DDDS_INITIAL_FREQUENCY_2,	0xff},	   //446 (DDS_LO)
	{DDDS_COMP_FRACTION_0,			0xff},	   //448 (DDS_LO)
	{DDDS_COMP_FRACTION_1,			0xff},	   //449 (DDS_HI)
	{DDDS_COMP_FRACTION_2,			0xff},	   //450 (DDS_LO)
	{DDDS_COMP_INTEGER_0,			0xff},	   //451 (DDS_HI)
	{DDDS_COMP_INTEGER_1,			0xf },	   //452 (DDS_LO)
	{DDDS_REF_LINE_VAL_0,			0xff},	   //454 (DDS_LO)
	{DDDS_REF_LINE_VAL_1,			0xf },	   //455 (DDS_HI)
	{DDDS_FREQUENCY_DELTA_THRESH,	0xff},	   //456 (DDS_LO)
	//{DDDS_TRACKING_ERR,			0xff},	   //457 (DDS_HI)
	//{DDDS_FREQ_0,					0xff},	   //458 (DDS_LO)
	//{DDDS_FREQ_1,					0xff},	   //459 (DDS_HI)
	//{DDDS_FREQ_2,					0xff},	   //460 (DDS_LO)
	{DDDS_ESM_CTRL,					0xff},	   //462 (DDS_LO)
	#ifdef DDDS_TEST_CTRL
	{DDDS_TEST_CTRL,					0x3 },	   //463 (DDS_HI)
	#endif // DDDS_TEST_CTRL
	//{DDDS_TEST_DATA_0,				0xff},	   //464 (DDS_LO)
	//{DDDS_TEST_DATA_1,				0xff},	   //465 (DDS_HI)
	//{DDDS_TEST_DATA_2,				0xff},	   //466 (DDS_LO)
	{OP_ENABLE,							0xff},	   //480 (DP_LO)
	#ifdef DP_POLARITY
	{DP_POLARITY,						0xf },	   //481 (DP_HI)
	#endif // DP_POLARITY
	{DISPLAY_CONTROL,					0x27},	   //482 (DP_LO)
	{DH_TOTAL_0,						0xff},	   //484 (DP_LO)
	{DH_TOTAL_1,						0xf },	   //485 (DP_HI)
	{DH_HS_END,							0x7f},	   //487 (DP_HI)
	{DH_BKGND_START_0,				0xff},	   //488 (DP_LO)
	{DH_BKGND_START_1,				0xf },	   //489 (DP_HI)
	{DH_ACTIV_START_0,				0xff},	   //490 (DP_LO)
	{DH_ACTIV_START_1,				0xf },	   //491 (DP_HI)
	{DH_ACTIV_WIDTH_0,				0xff},	   //492 (DP_LO)
	{DH_ACTIV_WIDTH_1,				0xf },	   //493 (DP_HI)
	#ifdef DH_WIN_START_0
	{DH_WIN_START_0,					0xff},	   //494 (DP_LO)
	{DH_WIN_START_1,					0xf },	   //495 (DP_HI)
	{DH_WIN_WIDTH_0,					0xff},	   //496 (DP_LO)
	{DH_WIN_WIDTH_1,					0xf },	   //497 (DP_HI)
	#endif //DH_WIN_START_0
	{DH_BKGND_END_0,					0xff},	   //498 (DP_LO)
	{DH_BKGND_END_1,					0xf },	   //499 (DP_HI)
	{DV_TOTAL_0,						0xff},	   //500 (DP_LO)
	{DV_TOTAL_1,						0x7 },	   //501 (DP_HI)
	{DV_VS_END,							0xf },	   //502 (DP_LO)
	{DV_BKGND_START_0,				0xff},	   //504 (DP_LO)
	{DV_BKGND_START_1,				0x7 },	   //505 (DP_HI)
	{DV_ACTIV_START_0,				0xff},	   //506 (DP_LO)
	{DV_ACTIV_START_1,				0x7 },	   //507 (DP_HI)
	{DV_ACTIV_LENGTH_0,				0xff},	   //508 (DP_LO)
	{DV_ACTIV_LENGTH_1,				0x7 },	   //509 (DP_HI)
	#ifdef DV_WIN_START_0
	{DV_WIN_START_0,					0xff},	   //510 (DP_LO)
	{DV_WIN_START_1,					0x7 },	   //511 (DP_HI)
	{DV_WIN_LENGTH_0,					0xff},	   //512 (DP_LO)
	{DV_WIN_LENGTH_1,					0x7 },	   //513 (DP_HI)
	#endif //DV_WIN_START_0
	{DV_BKGND_END_0,					0xff},	   //514 (DP_LO)
	{DV_BKGND_END_1,					0x7 },	   //515 (DP_HI)
	{BKGND_RED,							0xff},	   //516 (DP_LO)
	{BKGND_GRN,							0xff},	   //517 (DP_HI)
	{BKGND_BLU,							0xff},	   //518 (DP_LO)
	{DP_FLAGLINE_0,					0xff},	   //520 (DP_LO)
	{DP_FLAGLINE_1,					0x7 },	   //521 (DP_HI)
	//{DV_POSITION_0,					0xff},	   //522 (DP_LO)
	//{DV_POSITION_1,					0x7 },	   //523 (DP_HI)
	//{PANEL_POWER_STATUS,			0x3 },	   //524 (DP_LO)
	{PANEL_PWR_UP_T1,					0xff},	   //525 (DP_HI)
	{PANEL_PWR_UP_T2,					0xff},	   //526 (DP_LO)
	{PANEL_PWR_DN_T1,					0xff},	   //527 (DP_HI)
	{PANEL_PWR_DN_T2,					0xff},	   //528 (DP_LO)
	{DP_SYNC_ADJUST_CTRL,			0xf },	   //529 (DP_HI)
	{ALT_DISP_HTOTAL_DELTA_0,		0xff},	   //530 (DP_LO)
	{ALT_DISP_HTOTAL_DELTA_1,		0xf },	   //531 (DP_HI)
	{ALT_DISP_VTOTAL_0,				0xff},	   //532 (DP_LO)
	{ALT_DISP_VTOTAL_1,				0x7 },	   //533 (DP_HI)
	{ALT_DISP_ADJ_LINES,				0x3f},	   //534 (DP_LO)
	{DST_FREE_RUN_CNTRL,				0xff},	   //535 (DP_HI)
	#ifdef RGB2YUV_CTRL
	{RGB2YUV_CTRL,						0x3 },	   //544 (CC_LO)
	{YC_LINK_CTRL,						0x3 },	   //546 (CC_LO)
	{YCL_MAX_DELTA,					0xf },	   //547 (CC_HI)
	{YCL_SCL_THRESHOLD,				0x7f},	   //548 (CC_LO)
	{YCL_SCALE,							0xff},	   //549 (CC_HI)
	#endif //RGB2YUV_CTRL
	#if USE_ACC_ACM
	{ACC_CTRL,							0x1f},	   //550 (CC_LO)
	{ACC_SNAP_SLOPE,					0xff},	   //5