📄 appstest.c
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gm_ReadNVRAMAbsolute(NvramAddr,RdCmd->BUF,Length);
gm_CommsSendReply( RdCmd, comm_use);
NVRAM_Unlock = 0;
return;
}
if((NVRAM_Unlock != sizeof(UnlockSeq)) && (NvramAddr == UnlockSeq[NVRAM_Unlock]))
{
NVRAM_Unlock++;
if(NVRAM_Unlock == sizeof(UnlockSeq))
{// once special unlock sequence has been performed, the next NvramWrite
// will be to a specific BLOCK_ID which is passed in through the address.
msg("NVRAM unlock, next write will be to NVRAM Block",0);
}
}
else
NVRAM_Unlock = 0;
Length = CmdPtr->length;
RdCmd->cmd = Cmd;
RdCmd->len = Length + 3;
gm_ReadNVRAMAbsolute(NvramAddr,RdCmd->BUF,Length);
gm_CommsSendReply( RdCmd, comm_use);
}
//******************************************************************
// FUNCTION : NvramWr
// USAGE : Write an NVRAM byte/s
// DESCRIPTION : This function writes bytes to NVRAM.
// ** This function relies on the commhandler WrRamBurst function **
// INPUT : None
// OUTPUT : None
// GLOBALS : None
// USED_REGS : None
//******************************************************************
static BYTE BlockNvramWr(WrNvramBlockCmd_t *CmdPtr)
{
WORD length,src_addr,dst_addr;
BYTE temp;
length = GetWordFromBuffer(&CmdPtr->Length);
dst_addr = GetWordFromBuffer(&CmdPtr->NvramAddr);
src_addr = GetWordFromBuffer(&CmdPtr->RamAddr);
if(NVRAM_Unlock == sizeof(UnlockSeq))
{// once special unlock sequence has been performed, the next NvramWrite
// will be to a specific BLOCK_ID which is passed in through the address.
NVRAM_Unlock = 0;
msg("unlock, writing NVRAM block %d",dst_addr);
temp = *(BYTE *)src_addr;
return gm_WriteNVRAMBlock((BYTE)dst_addr, 0x00, (BYTE *)src_addr, 0x00, length);
}
while(length--)
{
temp = *(BYTE *)src_addr;
gm_WriteNVRAMAbsolute(dst_addr,&temp,0x01);
src_addr++;
dst_addr++;
}
return gmd_TRUE;
}
static WORD GetWordFromBuffer(void *buff)
{
WORD temp;
temp = ((BYTE *)buff)[0];
temp <<= 8;
temp |= ((BYTE *)buff)[1];
return temp;
}
#if ProcessExceptions != DisableExceptions
static void CheckExceptions(void)
{
if(exceptionFound)
{
msg("!!! E x c e p t i o n Encountered!!! 0x%x",exceptionFound);
exceptionFound = 0;
#if ProcessExceptions == ReportExceptions
DumpExceptionStack();
#endif
}
}
#endif
#if ProcessExceptions == ReportExceptions
static void DumpExceptionStack(void)
{
int Index;
msg("Codeseg at time of exception: 0x%x",savestack[exception_cs]);
msg("instruction pointer at time of exception: 0x%x",savestack[exception_ip]);
msg("dumping %d elements of stack at time of exception",Exception_STACKSIZE);
for ( Index = 0; Index < Exception_STACKSIZE; Index++)
{
msg("0x%x",savestack[Index]);
}
}
#endif
#if !REMOVE_APPSTEST
//******************************************************************************
//************ Memory test function ********************************************
//******************************************************************************
static WORD doApps_MemTest(int AddrIncType)
{
int result;
// Disable Interrupts
gm_DisableInterrupts();
asm {
//
//get the address and length from Global Variables
//
push bx
push dx
push cx
mov ax, es
push ax
//
//get the address and length from Global Variables
mov cx, TestMemLength
les bx, TestMem
//
MemLoop:
//
// Save the memory contents
mov dx,word ptr es:[bx]
//
// Check testpattern0
mov word ptr es:[bx],TEST_PATTERN_0
cmp WORD ptr es:[bx],TEST_PATTERN_0
jne FailTest
//
// Check for test pattern 1
mov word ptr es:[bx],TEST_PATTERN_1
cmp word ptr es:[bx],TEST_PATTERN_1
jne FailTest
//
// Restore the memory contents
mov word ptr es:[bx],dx
//
// Inc/Dec the address
mov ax, AddrIncType
or ax, ax
jnz DecAddrs
mov ax, es
add bx, 2
adc ax, 0
mov es, ax
jmp ChkLoop
DecAddrs:
mov ax, es
sub bx, 2
jnc ChkLoop
sub ax, 1
mov es, ax
//
// Loop back if more to check
ChkLoop:
loop MemLoop
//
// Test passed return 0
mov result, 0
jmp EndTest
//
FailTest:
// Restore the memory contents
mov word ptr es:[bx],dx
// Capture the address where test failed
mov ax, es
mov word ptr FailedMem+2, ax
mov word ptr FailedMem, bx
// Test failed, return non-zero.
mov result, 0xFFFF
EndTest:
pop dx
mov es, dx
pop cx
pop dx
pop bx
sti // Enable interrupts
}
return result;
}
//******************************************************************************
//************ 52xx register map ***********************************************
//******************************************************************************
typedef struct {
WORD reg; //if reg = 0xffff then mask = how many registers to skip.
BYTE mask;
} regMaskType;
regMaskType ROM regDesc[] =
{
// register, mask
//-------------------------------------------------------------------
//{HOST_CONTROL, 0x1f}, //0 (HOST_LO)
//{PRODUCT_ID, 0xff}, //1 (HOST_HI)
//{PRODUCT_REV, 0xff}, //2 (HOST_LO)
//{CLOCK_CONFIG, 0xff}, //3 (HOST_HI)
//{OCM_TCLK_DIV, 0xff}, //4 (HOST_LO)
//{LATCHED_BOOT, 0x3f}, //5 (HOST_HI)
{BYPASS, 0xf }, //6 (HOST_LO)
#ifdef TIMING_CONFIG
{TIMING_CONFIG, 0x7 }, //7 (HOST_HI)
{PADDRIVE1, 0xff}, //8 (HOST_LO)
{PADDRIVE2, 0xff}, //9 (HOST_HI)
{PADDRIVE3, 0xff}, //10 (HOST_LO)
#endif // TIMING_CONFIG
{IRQ_CONFIG, 0x17}, //11 (HOST_HI)
{IFM_OCMMASK, 0xdf}, //12 (HOST_LO)
{INPUT_OCMMASK, 0xff}, //13 (HOST_HI)
{MISC_OCMMASK, 0xdf}, //14 (HOST_LO)
//{SYSTEM_STATUS, 0x7c}, //15 (HOST_HI)
//{IFM_STATUS, 0xbf}, //16 (HOST_LO)
//{INPUT_STATUS, 0xff}, //17 (HOST_HI)
//{DISPLAY_STATUS, 0xff}, //18 (HOST_LO)
//{CLOCK_STATUS, 0x1f}, //19 (HOST_HI)
//{MISC_STATUS, 0x7 }, //20 (HOST_LO)
//{RCLK_CONFIG, 0x18}, //22 (DDS_LO)
//{RCLK_FREQUENCY, 0x7f}, //23 (DDS_HI)
//{RCLK_PLL, 0x67}, //24 (DDS_LO)
{FCLK_FREQ_0, 0xff}, //26 (DDS_LO)
{FCLK_FREQ_1, 0xff}, //27 (DDS_HI)
{LCLK_FREQ_0, 0xff}, //28 (DDS_LO)
{LCLK_FREQ_1, 0xff}, //29 (DDS_HI)
//{OCM_BUS_CONTROL_0, 0xf }, //32 (CORE_LO)
//{OCM_WBUF_STATUS, 0xf }, //33 (CORE_HI)
//{OCM_BUS_WDT_INIT_1, 0xff}, //34 (CORE_LO)
//{OCM_BUS_WDT_STATUS, 0x1 }, //35 (CORE_HI)
//{OCM_WDT_ERR_ADDR_0, 0xff}, //36 (CORE_LO)
//{OCM_WDT_ERR_ADDR_1, 0xff}, //37 (CORE_HI)
//{OCM_WDT_ERR_ADDR_2, 0xf }, //38 (CORE_LO)
//{OCM_CONTROL, 0x11}, //39 (HOST_HI)
#ifdef EXT_ROM_WR_CTRL
{EXT_ROM_WR_CTRL, 0x7f}, //40 (CORE_LO)
{EXT_ROM_RD_CTRL, 0x1f}, //41 (CORE_HI)
#endif // EXT_ROM_WR_CTRL
//{SPI_CONTROL, 0xff}, //42 (CORE_LO)
//{SPI_STATUS, 0x7 }, //43 (CORE_HI)
//{SPI_DATA_0, 0xff}, //44 (CORE_LO)
//{SPI_DATA_1, 0xff}, //45 (CORE_HI)
//{SPI_CACHE_CTRL, 0xf }, //46 (CORE_LO)
{PWM0_CONFIG, 0x7f}, //48 (HOST_LO)
{PWM0_PERIOD, 0xff}, //49 (HOST_HI)
{PWM0_PULSE, 0xff}, //50 (HOST_LO)
{PWM1_CONFIG, 0x7f}, //51 (HOST_HI)
{PWM1_PERIOD, 0xff}, //52 (HOST_LO)
{PWM1_PULSE, 0xff}, //53 (HOST_HI)
#ifdef PWM2_CONFIG
{PWM2_CONFIG, 0x7f}, //54 (HOST_LO)
{PWM2_PERIOD, 0xff}, //55 (HOST_HI)
{PWM2_PULSE, 0xff}, //56 (HOST_LO)
{PWM3_CONFIG, 0x7f}, //57 (HOST_HI)
{PWM3_PERIOD, 0xff}, //58 (HOST_LO)
{PWM3_PULSE, 0xff}, //59 (HOST_HI)
#endif // PWM2_CONFIG
{GPIO_DIRCTRL1, 0xff}, //60 (HOST_LO)
{GPO_OPENDRAIN_EN1, 0xff}, //61 (HOST_HI)
//{GPINPUT1, 0xff}, //62 (HOST_LO)
{GPOUTPUT1, 0xff}, //63 (HOST_HI)
#ifdef GPIO_DIRCTRL3
{GPIO_DIRCTRL2, 0xff}, //64 (HOST_LO)
{GPO_OPENDRAIN_EN2, 0xff}, //65 (HOST_HI)
//{GPINPUT2, 0xff}, //66 (HOST_LO)
{GPOUTPUT2, 0xff}, //67 (HOST_HI)
{GPIO_DIRCTRL3, 0xff}, //68 (HOST_LO)
#ifndef PHOENIX_U
{GPO_OPENDRAIN_EN3, 0xff}, //69 (HOST_HI)
#endif
//{GPINPUT3, 0xff}, //70 (HOST_LO)
{GPOUTPUT3, 0xff}, //71 (HOST_HI)
#endif // GPIO_DIRCTRL2
{LOW_BW_ADC_CTRL, 0x7f}, //72 (HOST_LO)
//{LOW_BW_ADC_RESULT, 0xff}, //73 (HOST_HI)
//{LOW_BW_ADC_STATUS, 0x1 }, //74 (HOST_LO)
{LOW_BW_ADC_TEST, 0x3 }, //75 (HOST_HI)
//{I2C_MST_CTRL, 0xf }, //80 (OCM_LO)
#ifdef I2C_MST_DMA_CNTR
{I2C_MST_DMA_CNTR, 0xff}, //81 (OCM_HI)
{I2C_MST_CLK_SCALE_0, 0xff}, //82 (OCM_LO)
{I2C_MST_CLK_SCALE_1, 0xff}, //83 (OCM_HI)
//{I2C_MST_TX_CTRL, 0xf9}, //84 (OCM_LO)
{I2C_MST_TX_DATA, 0xff}, //85 (OCM_HI)
//{I2C_MST_STATUS, 0xd3}, //86 (OCM_LO)
//{I2C_MST_RX_DATA, 0xff}, //87 (OCM_HI)
{VPORT_CTRL, 0x1 }, //88 (IP_LO)
#endif // I2C_MST_DMA_CNTR
{ADC_CONTROL, 0xff}, //96 (ADC_LO)
#ifdef PHOENIX_U
{ADC_RESERVED_0, 0x3f}, //97 (ADC_HI)
{ADC_RESERVED_1, 0x3f}, //98 (ADC_LO)
#else
{ADC_CLAMPSTART, 0x3f}, //97 (ADC_HI)
{ADC_CLAMPWIDTH, 0x3f}, //98 (ADC_LO)
#endif
#if !defined(GSEL_BUILD) && !defined(APP_BUILD)
{ADC_FAS0, 0xff}, //100 (ADC_LO)
{ADC_FAS1, 0xff}, //101 (ADC_HI)
#else // latest universal register names used in GSEL
{ADC_FAS1, 0xff}, //100 (ADC_LO)
{ADC_FAS2, 0xff}, //101 (ADC_HI)
#endif
{ADC_TEST1, 0xff}, //102 (ADC_LO)
{ADC_TEST2, 0xff}, //103 (ADC_HI)
//{ADC_DATA_RED, 0xff}, //104 (ADC_LO)
//{ADC_DATA_GRN, 0xff}, //105 (ADC_HI)
//{ADC_DATA_BLU, 0xff}, //106 (ADC_LO)
//{ADC_FLAGS, 0x3f}, //107 (HOST_HI)
{RED_OFFSET1, 0x3f}, //108 (ADC_LO)
{RED_OFFSET2, 0x7f}, //109 (ADC_HI)
{RED_GAIN_0, 0xff}, //110 (ADC_LO)
{RED_GAIN_1, 0x1 }, //111 (ADC_HI)
{GRN_OFFSET1, 0x3f}, //112 (ADC_LO)
{GRN_OFFSET2, 0x7f}, //113 (ADC_HI)
{GRN_GAIN_0, 0xff}, //114 (ADC_LO)
{GRN_GAIN_1, 0x1 }, //115 (ADC_HI)
{BLU_OFFSET1, 0x3f}, //116 (ADC_LO)
{BLU_OFFSET2, 0x7f}, //117 (ADC_HI)
{BLU_GAIN_0, 0xff}, //118 (ADC_LO)
{BLU_GAIN_1, 0x1 }, //119 (ADC_HI)
{ADC_TESTDAC, 0xff}, //120 (ADC_LO)
{ADC_DAC_DATA, 0xff}, //121 (ADC_HI)
{ADC_MODULATION, 0xff}, //122 (ADC_LO)
{MISSING_CODE_TEST, 0xff}, //123 (ADC_HI)
#ifdef ADC_RG_PHASE
{ADC_RG_PHASE, 0x33}, //124 (ADC_LO)
#else
{ADC_RGB_PHASE, 0x3f}, //124 (ADC_LO)
#endif // ADC_RG_PHASE
{SYNC_TIP_CLAMP_END, 0xff}, //125 (ADC_HI)
{SYNC_TIP_CLAMP_TIME_OUT, 0xff}, //126 (ADC_LO)
#if !defined(TUCSON)
{DVI_CTRL, 0xfe}, //128 (IP_LO)
{DVI_EQUALIZATION, 0xff}, //129 (IP_HI)
{DVI_CONFIG, 0xff}, //130 (IP_LO)
{DVI_DE, 0xff}, //131 (IP_HI)
{DVI_PLL, 0xff}, //132 (IP_LO)
#ifdef DVI_PHASEPICK3
{DVI_PHASEPICK3, 0xf }, //133 (IP_HI)
{DVI_PHASEPICK2, 0xff}, //134 (IP_LO)
{DVI_PHASEPICK1, 0xff}, //135 (IP_HI)
#endif // DVI_PHASEPICK3
{DVI_MISC, 0xfc}, //136 (IP_LO)
#ifdef DVI_TESTCTRL
{DVI_TESTCTRL, 0x18}, //137 (IP_HI)
#else
{DVI_TESTCTRL, 0x1f}, //137 (IP_HI)
#endif
{DVI_TEST, 0x1f}, //138 (IP_LO)
{DVI_PHASE_ADJ, 0x3f}, //139 (IP_HI)
#endif // #if !defined(TUCSON)
//{DVI_SIGQUAL_0, 0xff}, //140 (IP_LO)
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