52xx-init.c

GM5621原代码

		}
		gm_WriteRegByte(LVDS_CLK_DATA,   0x1e);
		gm_WriteRegByte(LVDS_PLL_CTRL,	0x30);
		gm_WriteRegByte(LVDS_MISC_CTRL,	0x40);
		gm_WriteRegByte(LVDS_P2S_CTRL0,	0x1e);
		gm_WriteRegByte(LVDS_P2S_CTRL1,	0x08);
		gm_WriteRegByte(LVDS_TEST_CTRL,	0);
		gm_WriteRegByte(LVDS_TEST_DATA,	0);
	}
#else
	#ifdef	LVDS_PANEL
		#if (PanelDepth == 8)
				gm_WriteRegByte(LVDS_POWER, TTL_LVDS_SEL | LVDS_BIAS_EN | LVDS_PLL_EN | LVDS_DRIVER_EVEN_EN | OddEn | LVDDS_CH3_EN);
				gm_WriteRegByte(LVDS_DIGITAL_CTRL, POS_NEG_SWAP | (Panel_LVDSBus_EvenOddSwap << EVEN_ODD_SWAP_SHIFT) | (Panel_LVDS_BusType << DUAL_BUS_EN_SHIFT) | EIGHT_BIT_MODE_SEL);
		#else
				gm_WriteRegByte(LVDS_POWER, TTL_LVDS_SEL | LVDS_BIAS_EN | LVDS_PLL_EN | LVDS_DRIVER_EVEN_EN | OddEn);
				gm_WriteRegByte(LVDS_DIGITAL_CTRL, POS_NEG_SWAP | (Panel_LVDSBus_EvenOddSwap << EVEN_ODD_SWAP_SHIFT) | (Panel_LVDS_BusType <<DUAL_BUS_EN_SHIFT ));
		#endif
		gm_WriteRegByte(LVDS_CLK_DATA,   0x1e);
		gm_WriteRegByte(LVDS_PLL_CTRL,	0x30);
		gm_WriteRegByte(LVDS_MISC_CTRL,	0x40);
		gm_WriteRegByte(LVDS_P2S_CTRL0,	0x1e);
		gm_WriteRegByte(LVDS_P2S_CTRL1,	0x08);
		gm_WriteRegByte(LVDS_TEST_CTRL,	0);
		gm_WriteRegByte(LVDS_TEST_DATA,	0);
	#endif
#endif

	  // Move to here for panel check (fix panel array complie error issue). 0401 
	gmc_PanelDepth = PanelDepth;
	if(gmc_PanelDepth == 8)              
		gm_WriteRegByte(MULT_DITHER_CTRL, (MULT_DITH_TRUNC | MULT_DITH_1FRAME));
    	else
  		gm_WriteRegByte(MULT_DITHER_CTRL, MULT_DITH_SPATIAL);
	gm_WriteRegByte(HOST_CONTROL,		IPFORCE_UPDATE | DPFORCE_UPDATE);

// check the panel parameters and give compile error if necessary
#if USING_PANEL_ARRAY
	if((PanelHActiveStart+PanelWidth+PanelMinHSyncFrontPorch) > PanelMinHTotal)
	{
		msg("WARNING : Panel Horizontal Total value is too small!, %d", PanelMinHTotal);
		msg("B_PanelIndex %d", B_PanelIndex);
		msg("PanelHActiveStart, %d", PanelHActiveStart);
		msg("PanelWidth, %d", PanelWidth);
		msg("PanelMinHSyncFrontPorch, %d", PanelMinHSyncFrontPorch);
		gm_Delay100ms(100);
	}
	if((PanelVActiveStart+PanelHeight+PanelMinVSyncFrontPorch) > PanelMinVTotal)
	{
		msg("WARNING : Panel Vertical Total value is too small!, %d", PanelMinVTotal);
		msg("B_PanelIndex %d", B_PanelIndex);
		msg("PanelHActiveStart, %d", PanelVActiveStart);
		msg("PanelWidth, %d", PanelHeight);
		msg("PanelMinHSyncFrontPorch, %d", PanelMinVSyncFrontPorch);
		gm_Delay100ms(100);
	}
#else
	#if ((PanelHActiveStart+PanelWidth+PanelMinHSyncFrontPorch) > PanelMinHTotal)
		#error ( WARNING : Panel Horizontal Total value is too small!)
	#endif

	#if ((PanelVActiveStart+PanelHeight+PanelMinVSyncFrontPorch) > PanelMinVTotal)
		#error ( WARNING : Panel Vertical Total value is too small!)
	#endif
#endif // USING_PANEL_ARRAY

	// initialize registers based on panel array variables.  Run time variables
	// can not be initialized through gm_WriteRegBlock.
	gm_WriteRegByte(DDDS_CONTROL, ( 4 << D_K_DIFF_SHIFT) | (4 <<D_K_MAIN_SHIFT) | (Panel_Spread_Spect_En << SPREAD_SP_EN_SHIFT));
	gm_WriteRegByte(DDDS_ESM_CTRL, PanelSpreadSpectrumCtrl);
	//DDDS_INIT	start ddds
	gm_WriteRegByte(DDDS_INIT,1);

}
//******************************************************************
// STRUCTURE    :   SystemInitBlock
// USAGE        :   Describes required initial register cotent
// DESCRIPTION  :   -Initializes system clocks
//                  -DDS's (digital PLL's)
//                  -type of update for the used registers
//                  -GPIO registers
//                  -ADC  registers
//                  -DVI registers
//                  -Display registers
//
//******************************************************************
gm_DefineRegBlock(SystemInitBlock)

	/********************************************************************/
	/*	Initialize:  GPIO                                    			*/
	/********************************************************************/
#if	PWM0_BRIGHTNESS==1
	// enable output and use TCLK/512 as clock
	RB_WriteByte( PWM0_CONFIG,		PWM0_GPIOn_EN | PWM0_CLKSEL | PWM0_TCLK_DIV),
	RB_WriteByte( PWM0_PERIOD,		0xFF), // set period to max ie. about 54.62 hz for 14.318 Mhz tclk
#else
	RB_WriteByte( PWM0_CONFIG, 		0x00), // configure pmw0 as gpio0, backlight
#endif
	RB_WriteByte( PWM1_CONFIG, 		0x00), // configure pmw1 as gpio1, led grn

#if ((BOARD == EV_BD) || (BOARD == RD1C_BD) || (BOARD == FPGA_BOARD) || (BOARD == RD5))
	RB_WriteByte(GPIO_DIRCTRL1, 		GPIO1_MASK),
	RB_WriteByte(GPIO_DIRCTRL2, 		0x00),	// used for panel
	RB_WriteByte(GPO_OPENDRAIN_EN1, 	GPIO1_ODEN),
	RB_WriteByte(GPO_OPENDRAIN_EN2, 	0x00),

#if (LED_POL == POS_POL)
	RB_WriteByte(GPOUTPUT1, 			GPIO1_MASK),
#else
   RB_WriteByte(GPOUTPUT1, 			0),
#endif

#endif

	/********************************************************************/
	/*	Initialize:  SYSMASKs						                    */
	/********************************************************************/
	//BYPASS	normal scaler operation	0
	RB_WriteByte(BYPASS, 0x00),
	//IRQ_CONFIG	Disable IRQ	0
	RB_WriteByte(IRQ_CONFIG, 0x00),
	//IFM_SYSMASK	set No Hsync/Vsync, Hs/Vs period err, Interlaced line counter err. 	0x8F
	RB_WriteByte(IFM_OCMMASK, (NO_HS | NO_VS | HS_PERIOD_ERR | VS_PERIOD_ERR | INTLC_ERR)),
	//INPUT_SYSMASK	set IP_VS and IP_OVERRUN	0x18
	//MISC_SYSMASK	set D_VS and CLK_EVENT	0x48
	RB_WriteByte(MISC_OCMMASK, (CLK_EVENT | D_VS_FLAG)),

	//Set Schmitt Trigger hysteresis for Set2 (0x82a1=4)
	#ifdef USE_HYSTERESIS_SEL
	RB_WriteByte(TEST_CTRL_1, HYSTERESIS_SEL),
	#endif
	/********************************************************************/
	/*	Initialize:  DDS                           						*/
	/********************************************************************/
	//DDS_CONTROL	Force SDDS and DDDS to Open Loop and enable SDDS, DDDS, FCLK, LCLK
	RB_WriteByte(DDS_CONTROL, (FORCE_SDDS_OPLOOP | FORCE_DDDS_OPLOOP | SDDS_ENABLE | DDDS_ENABLE | FCLK_ENABLE | ACLK2_ENABLE | LCLK_ENANLE)),

	/********************************************************************/
	/*	Initialize:  SDDS                          						*/
	/********************************************************************/
	//SDDS_CONTROL	For normal operation program the constant value 0x93. No Hsync Corr	0x92
	RB_WriteByte(SDDS_CONTROL,	(K_MAIN << K_MAIN_SHIFT) | (K_DIFF << K_DIFF_SHIFT)),
	//SDDS_INITIAL_FREQ	Set Initial Frequency of 80 MHz. (80/200) * 2**24 = 0x666666
	//RB_WriteTriBytes(SDDS_INITIAL_FREQ_HI,	0x666666),
	//SDDS_INITIAL_FREQ	Set Initial Frequency of 80 MHz. (80/214) * 2**24 = 0x5fb370
	RB_WriteDWord(SDDS_INITIAL_FREQ,	SDDS_INIT_FREQ_VAL),
	//SDDS_STEP_VAL	set sdds compare period step to ?? sclk period	0xC0
	RB_WriteByte(SDDS_STEP_VAL,INIT_SDDS_STEP_VAL),
	//SDDS_FREQ_THRESH	Write a value of "0"	0x00
	RB_WriteByte(SDDS_FREQUENCY_DELTA_THRESH, 0x00),
	//SDDS_INIT	start ddds
	RB_WriteByte(SDDS_INIT,1),
	// SDDS_TEST_CTRL1 set 6 for stable sclk in xga 85hz.
	RB_WriteByte(SDDS_TEST_CNTRL0, 0x00),
	RB_WriteByte(SDDS_TEST_CNTRL1, 10),

	/********************************************************************/
	/*	Initialize:  DDDS                          						*/
	/********************************************************************/
	//DDDS_CONTROL	For normal operation program the constant value 0x90.
	//	SPREAD_SP_EN bit set based on panel 	0x90, or 0x92
	// DDDS_CONTROL moved to System_Init since contains run time variable
	// PanelSpread_Spect_En.
	//	RB_WriteByte(DDDS_CONTROL, ( 4 << D_K_DIFF_SHIFT) | (4 <<D_K_MAIN_SHIFT) | (SPREAD_SP_EN & Panel_Spread_Spect_En)),
	//DDDS_INITIAL_FREQ	Initial Freq to typical panel:
	//	(65/200) * 2**24 = 0x533333
	//RB_WriteTriBytes(DDDS_INITIAL_FREQ_HI, 0x533333),
	//	(65/214) * 2**24 = 0x4dc1cb
	RB_WriteDWord(DDDS_INITIAL_FREQ, DDDS_INIT_FREQ_VAL),
	//DDDS_FREQ_THRESH	Write a value of "0"	0x0
	RB_WriteByte(DDDS_FREQUENCY_DELTA_THRESH, 0x00),
	//DDDS_ESM_CTRL	Spread spectrum based on panel
	// DDDS_ESM_CTRL moved to System_Init since contains run time variable
	// PanelSpreadSpectrumCtrl.
	//	RB_WriteByte(DDDS_ESM_CTRL, PanelSpreadSpectrumCtrl),
	//DDDS_INIT	start ddds
	RB_WriteByte(DDDS_INIT,1),

	/********************************************************************/
	/*	Initialize:  ADC                           						*/
	/********************************************************************/
	//ADC_CONTROL	Automatically Detected for each SYNC type (0x5D When HS is active low,  invert it in ADC)	0x59
	RB_WriteByte(ADC_CONTROL,	(ADC_ENABLE | CLAMP_EN |	AC_COUPLE_EN |  ( SOG_SENSITIVITY  << SOG_SENS_SHIFT))),
	//SYNC_TIP_CLAMP_END	Default for all modes is 0x08	0x08
	RB_WriteByte(SYNC_TIP_CLAMP_END, 0x00),
	//SYNC_TIP_CLAMP_TIME_OUT	1.2 * longest line length / (16 * tclk) = 1.2 * 63.5 / (16 * 0.07) = 68 = 0x44	0x44
	RB_WriteByte(SYNC_TIP_CLAMP_TIME_OUT, 0x44),
	//ADC_CLAMP_START	Clamp start is programmed to 1  	0X01
	RB_WriteByte(ADC_CLAMPSTART, 0x00), // 0x01
	//ADC_CLAMPWIDTH	Clam Width is programmed to 2. 	0X02
	RB_WriteByte(ADC_CLAMPWIDTH, 0x01), // 0x02
	//ADC_FAS_hi/lo	constant to 0x040C	0x040C
	RB_WriteByte(ADC_FAS1, MSB_CLMP),
	RB_WriteByte(ADC_FAS2, 0x03 << ADC_BW_SHIFT),
	//ADC_TEST_hi/lo	constant to 0x0010	0x0010
	RB_WriteByte(ADC_TEST1, 0x00),
	RB_WriteByte(ADC_TEST2, DIS_RACLK | I_BIAS),
	//ADC_MODULATION	set to 0 before it perform the adc linearity calibration	0x00
	//	RB_WriteByte(ADC_MODULATION, 0x00),

   // Set CDAC_GN before performing ADC Linearity.
	RB_WriteByte(MISSING_CODE_TEST, CDAC_GN),


	/********************************************************************/
	/*	Initialize:  DVI                           						*/
	/********************************************************************/
	RB_WriteByte(DVI_CTRL,          (RTERM_MAN |  ( RTERM_49Ohm << RTERM_SHIFT ))),
	RB_WriteByte(DVI_EQUALIZATION,  0x00 ), //set equalizer freq response to normal ( < 1m cable)
	RB_WriteByte(DVI_CONFIG,        PWRUP_STANDBY | MANPHASE_EN | RX_FREQ_HIGH ), //Stay in standby state
	RB_WriteByte(DVI_PLL,           DLPF | BW_4M | (0x02 << MS_SHIFT)),
	RB_WriteByte(DVI_DE, 	        DE_THRESHOLD_64  | DE_SEL_ALL), // | (3 << PHASE_SEL_SHIFT)
	RB_WriteByte(CLKMEAS_CONTROL,   CLKMEAS_WIDTH_256 | CLKMEAS_SRC_DVI),

	/********************************************************************/
	/*	Initialize:  IP and IFM                    						*/
	/********************************************************************/
	//IP_CONTROL	enable input capture 	0x04
	RB_WriteByte(IP_CONTROL, IP_RUN_EN | IP_SOURCE_RGB),
	//IPH_ACT_START	programmed with constant value 8
	RB_WriteWord(IPH_ACT_START, 		IPHS_ActiveStart),
	//IPV_ACT_START_ODD	constant to 10
	RB_WriteWord(IPV_ACT_START_ODD, 	IPVS_ActiveStart),
	//IPV_ACT_START_EVEN	constant to 10
	RB_WriteWord(IPV_ACT_START_EVEN, IPVS_ActiveStart),
	//SRC_VTOTAL	panel typical Vtotal	806
	RB_WriteWord(SRC_VTOTAL, 0),
	//IP_FLAGLINE	initial constant to 0x01	0x01
	RB_WriteWord(IP_FLAGLINE, 1),
	//CSYNC_CONTROL	Automatically Detected for each SYNC type	0x4E
	RB_WriteByte(CSYNC_CONTROL,	 HSRAW_DIS | CSYNC_SAMPLE4),

    RB_WriteByte(IFM_CTRL, INT_MODE_SEL | IFM_MEASEN | IFM_EN | INT_ODD_EN | IFM_HOFFSETEN),

	//IFM_WATCHDOG, program with large enough values to cover C-sync modes
	//which don't have Hsync pulses during the Vsync.
	RB_WriteByte(IFM_WATCHDOG, 	0x46),

	//IFM_FIELD_CONTROL	Fixed value. based on 14.3Mhz Tclk	0x20
	RB_WriteByte(IFM_FIELD_CONTROL, 	0x30),
	//IFM_HLINE	Fixed value to 0x0040	0x0040
	RB_WriteWord(IFM_HLINE, 		0x0040),
	//IFM_CHANGE	Fixed to Threshold of 8	0x24
	//RB_WriteByte(IFM_CHANGE, 	IFM_CHG_THRESH_8 | (IFM_CHG_THRESH_8 << V_CHG_THRESH_SHIFT)),
	// #PDR14327,  Add DVI DE change threshold level (DE_CHG_THRESH)  for DVI DE jitter issue (Default 0), Louis 010305
	RB_WriteByte(IFM_CHANGE, 	IFM_CHG_THRESH_8 | (IFM_CHG_THRESH_8 << V_CHG_THRESH_SHIFT) | (DE_CHG_THRESH_0 << DE_CHG_THRESH_SHIFT)),

    RB_WriteByte(IBD_CONTROL, 	(IBD_THRESH_32 << DET_THOLD_SHIFT) | (RGB_SEL_RGB << RGB_SEL_SHIFT)),
	//SUMDIFF_MINMAX	initially 0x07. Used for auto adjust	0x07
	RB_WriteByte(SUMDIFF_MINMAX, 	0x07),
	//SUMDIFF_THRESHOLD	Fixed to 0x02	0x02
	RB_WriteByte(SDIFF_THRESHOLD, 0x02),

	RB_WriteByte(ALT_DISP_ADJ_LINES, 32),//8),

	/********************************************************************/
	/*	Initialize:  FILTER                        						*/
	/********************************************************************/
    // set LCLK to 10% higher than maximum panal clock (dclk)
	 RB_WriteWord(LCLK_FREQ, ((LCLK_MHZ << 16) / RCLK_MHZ)),
	RB_WriteByte(FILTER_CONTROL, LCLK_SEL | FILTER_MODE),
	RB_WriteByte(HOR_INIT_PHASE, 0x10),
	RB_WriteByte(VERT_INIT_PHASE, 0x10),
	RB_WriteByte(HOR_ALT_PHASE, 0x10),
	RB_WriteByte(VERT_ALT_PHASE, 0x1F),

	RB_WriteByte(DP_SYNC_ADJUST_CTRL, DP_ADJ_AUTO_EN),

	RB_WriteByte(CCF_TESTREG, (OSD_4BPP_FIX_DISABLE | THRESH_OPT)),

   // 0401 Move to Panel segment
  // #if (PanelDepth == 8)
  //		RB_WriteByte(MULT_DITHER_CTRL, (MULT_DITH_TRUNC | MULT_DITH_1FRAME)),
   //#else
  //		RB_WriteByte(MULT_DITHER_CTRL, MULT_DITH_SPATIAL),
   //#endif

	// Panel parameter init has been moved to InitPanelParameters() above
	// since panel parameters are now run time variables, and can not be
	// initiaized with gm_WriteRegBlock routine.

RB_WriteByteEnd(HOST_CONTROL,	IPFORCE_UPDATE | DPFORCE_UPDATE)

//******************************************************************
// FUNCTION    :  gm_Print
// DESCRIPTION :	If debugging using JTAG, then we don't want any
//						UART activity since they share the same port pins.
//						if DEBUG_JTAG is enabled, then this gm_Print function
// 					will override the GSEL gm_Print function and effectively
//						stop all prints.
//******************************************************************
#if (DEBUG_JTAG == 1)
#pragma warn -par
void far gm_Print (const char far *Bp_Str, WORD W_Value)
{
	return;
}
#pragma warn +par
#endif