📄 57xx-init.c
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gm_WriteRegByte(TCON_BLANKING_HOFFSET_1, ((TConBlankingHOffset & 0xf00) >> 8));
gm_WriteRegByte(LP_HSTART_0, TConLpHStart & 0xff);
gm_WriteRegByte(LP_HSTART_1, ((TConLpHStart & 0xf00) >> 8));
gm_WriteRegByte(LP_HEND_0, TConLpHEnd & 0xff);
gm_WriteRegByte(LP_HEND_1, ((TConLpHEnd & 0xf00) >> 8));
gm_WriteRegByte(ESP_HSTART_0, TConESPHStart & 0xff);
gm_WriteRegByte(ESP_HSTART_1, ((TConESPHStart & 0xf00) >> 8));
gm_WriteRegByte(ESP_WIDTH, TConESPWidth);
gm_WriteRegByte(OSP_HSTART_0, TConOSPHStart & 0xff);
gm_WriteRegByte(OSP_HSTART_1, ((TConOSPHStart & 0xf00) >> 8));
gm_WriteRegByte(OSP_WIDTH, TConOSPWidth);
gm_WriteRegByte(POL_SWITCH_TIME_0, TConPolSwitchTime & 0xff);
gm_WriteRegByte(POL_SWITCH_TIME_1, ((TConPolSwitchTime & 0xf00) >> 8));
gm_WriteRegByte(ROWCLK_HSTART_0, TConRowClkHStart & 0xff);
gm_WriteRegByte(ROWCLK_HSTART_1, ((TConRowClkHStart & 0xf00) >> 8));
gm_WriteRegByte(ROWCLK_HEND_0, TConRowClkHEnd & 0xff);
gm_WriteRegByte(ROWCLK_HEND_1, ((TConRowClkHEnd & 0xf00) >> 8));
gm_WriteRegByte(RSP1_VSTART_0, TConRSP1VStart & 0xff);
gm_WriteRegByte(RSP1_VSTART_1, ((TConRSP1VStart & 0xf00) >> 8));
gm_WriteRegByte(RSP1_WIDTH, TConRSP1Width);
//gm_WriteRegByte(RSP2_VSTART_0, TConRSP2VStart & 0xff);
//gm_WriteRegByte(RSP2_VSTART_1, ((TConRSP2VStart & 0xf00) >> 8));
//gm_WriteRegByte(RSP2_WIDTH, TConRSP2Width);
gm_WriteRegByte(ROE1_HSTART_0, TConROE1HStart & 0xff);
gm_WriteRegByte(ROE1_HSTART_1, ((TConROE1HStart & 0xf00) >> 8));
gm_WriteRegByte(ROE1_HEND_0, TConROE1HEnd & 0xff);
gm_WriteRegByte(ROE1_HEND_1, ((TConROE1HEnd & 0xf00) >> 8));
//RB_WriteByte(FILTER_CONTROL_EXT, FILTER_COEFF_CTRL),
gm_WriteRegByte(POST_LUT_DITHER_CTRL, 0x1f);
gm_WriteRegByte(HOST_CONTROL, IPFORCE_UPDATE | DPFORCE_UPDATE);
}
#else
#error Panel Type not defined!!!
#endif //panel type
#endif //!USING_PANEL_ARRAY
//******************************************************************
// STRUCTURE : SystemInitBlock
// USAGE : Describes required initial register cotent
// DESCRIPTION : -Initializes system clocks
// -DDS's (digital PLL's)
// -type of update for the used registers
// -GPIO registers
// -ADC registers
// -DVI registers
// -Display registers
//
//******************************************************************
static void _near Write_SystemInitBlock(void)
{
/*********************************************************************/
/* Initialize: PWM */
/*********************************************************************/
#if PWM0_BRIGHTNESS == 1
// enable output and use TCLK/512 as clock
#ifdef PWM0_GPIOn_EN
gm_WriteRegByte( PWM0_CONFIG, PWM0_GPIOn_EN | PWM0_CLKSEL | PWM0_TCLK_DIV);
#else
gm_WriteRegByte( PWM0_CONFIG, PWM0_CLKSEL | PWM0_TCLK_DIV);
#endif
gm_WriteRegByte( PWM0_PERIOD, 0xFF); // set period to max ie. about 54.62 hz for 14.318 Mhz tclk
#else
gm_WriteRegByte( PWM0_CONFIG, 0x00); // configure pmw0 as gpio0, backlight
#endif
gm_WriteRegByte( PWM1_CONFIG, 0x00); // configure pmw1 as gpio1, led grn
/*********************************************************************/
/* Initialize: GPIO */
/*********************************************************************/
#ifndef RSDS_PANEL
gm_WriteRegByte(TEST_CTRL_0, 0x8); // GPIO24 to GPIO29 are configured as GPIO.
#endif
#ifdef GPIO1_OUT_MASK
//If using GPIO1, then disable TCON in BYPASS.
gm_WriteRegByte(BYPASS, (TCON_SIGNALS_OFF | TCON_LB_BYPASS));
//Clear output register bits which are outputs.
gm_WriteRegByte(GPOUTPUT1, 0x00);
//Enable output bits.
gm_WriteRegByte(GPIO_DIRCTRL1, GPIO1_OUT_MASK);
// Set ODEN
gm_WriteRegByte(GPO_OPENDRAIN_EN1, GPIO1_ODEN);
#else
#ifdef RSDS_PANEL
gm_WriteRegByte(BYPASS, 0);
#else
gm_WriteRegByte(BYPASS, TCON_LB_BYPASS);
#endif
#endif
/*********************************************************************/
/* Initialize: SYSMASKs */
/*********************************************************************/
//BYPASS normal scaler operation 0
// gm_WriteRegByte(BYPASS, 0x00);
//IRQ_CONFIG Disable IRQ 0
gm_WriteRegByte(IRQ_CONFIG, 0x00);
//IFM_SYSMASK set No Hsync/Vsync, Hs/Vs period err, Interlaced line counter err. 0x8F
gm_WriteRegByte(IFM_OCMMASK, (NO_HS | NO_VS | HS_PERIOD_ERR | VS_PERIOD_ERR | INTLC_ERR));
//INPUT_SYSMASK set IP_VS and IP_OVERRUN 0x18
//MISC_SYSMASK set D_VS and CLK_EVENT 0x48
// Louis 0914, for S/W AOC ... use display v blanking interrupt.
//gm_WriteRegByte(MISC_OCMMASK, (CLK_EVENT | D_VS_FLAG));
gm_WriteRegByte(MISC_OCMMASK, 0);
//Set Schmitt Trigger hysteresis for Set2 (0x82a1=4)
#ifdef USE_HYSTERESIS_SEL
gm_WriteRegByte(TEST_CTRL_1, HYSTERESIS_SEL);
#endif
/*********************************************************************/
/* Initialize: DDS */
/*********************************************************************/
//DDS_CONTROL Force SDDS and DDDS to Open Loop and enable SDDS, DDDS, FCLK, LCLK
gm_WriteRegByte(DDS_CONTROL, (FORCE_SDDS_OPLOOP | FORCE_DDDS_OPLOOP | SDDS_ENABLE | DDDS_ENABLE | FCLK_ENABLE | ACLK2_ENABLE | LCLK_ENANLE));
/*********************************************************************/
/* Initialize: SDDS */
/*********************************************************************/
//SDDS_CONTROL For normal operation program the constant value 0x93. No Hsync Corr 0x92
//gm_WriteRegByte(SDDS_CONTROL, (K_MAIN << K_MAIN_SHIFT) | (K_DIFF << K_DIFF_SHIFT)),
// 0x9c
gm_WriteRegByte(SDDS_CONTROL, 0x80 | K_MAIN_MASK);
//SDDS_INITIAL_FREQ Set Initial Frequency of 80 MHz. (80/200) * 2**24 = 0x666666
//RB_WriteTriBytes(SDDS_INITIAL_FREQ_HI, 0x666666),
//SDDS_INITIAL_FREQ Set Initial Frequency of 80 MHz. (80/214) * 2**24 = 0x5fb370
gm_WriteRegDWord(SDDS_INITIAL_FREQ, SDDS_INIT_FREQ_VAL);
//SDDS_FREQ_THRESH Write a value of "0" 0x00
gm_WriteRegByte(SDDS_FREQUENCY_DELTA_THRESH, 0x00);
//SDDS_INIT start ddds
gm_WriteRegByte(SDDS_INIT,1);
// SDDS_TEST_CTRL1 set 6 for stable sclk in xga 85hz.
gm_WriteRegByte(SDDS_TEST_CNTRL0, 0x00);
gm_WriteRegByte(SDDS_TEST_CNTRL1, 0x4A);
/********************************************************************/
/* Initialize: DDDS */
/********************************************************************/
//DDDS_CONTROL For normal operation program the constant value 0x90.
// SPREAD_SP_EN bit set based on panel 0x90, or 0x92
// DDDS_CONTROL moved to System_Init since contains run time variable
// PanelSpread_Spect_En.
// gm_WriteRegByte(DDDS_CONTROL, ( 4 << D_K_DIFF_SHIFT) | (4 <<D_K_MAIN_SHIFT) | (SPREAD_SP_EN & Panel_Spread_Spect_En)),
//DDDS_INITIAL_FREQ Initial Freq to typical panel:
// (65/200) * 2**24 = 0x533333
//RB_WriteTriBytes(DDDS_INITIAL_FREQ_HI, 0x533333),
// (65/214) * 2**24 = 0x4dc1cb
gm_WriteRegDWord(DDDS_INITIAL_FREQ, DDDS_INIT_FREQ_VAL);
//DDDS_FREQ_THRESH Write a value of "0" 0x0
gm_WriteRegByte(DDDS_FREQUENCY_DELTA_THRESH, 0x00);
//DDDS_ESM_CTRL Spread spectrum based on panel
// DDDS_ESM_CTRL moved to System_Init since contains run time variable
// PanelSpreadSpectrumCtrl.
// gm_WriteRegByte(DDDS_ESM_CTRL, PanelSpreadSpectrumCtrl);
//DDDS_INIT start ddds
gm_WriteRegByte(DDDS_INIT,1);
/********************************************************************/
/* Initialize: ADC */
/********************************************************************/
//ADC_CONTROL Automatically Detected for each SYNC type (0x5D When HS is active low, invert it in ADC) 0x59
gm_WriteRegByte(ADC_CONTROL, (ADC_ENABLE | CLAMP_EN | AC_COUPLE_EN | ( SOG_SENSITIVITY << SOG_SENS_SHIFT)));
//SYNC_TIP_CLAMP_END Default for all modes is 0x08 0x08
gm_WriteRegByte(SYNC_TIP_CLAMP_END, 0x08);
//SYNC_TIP_CLAMP_TIME_OUT 1.2 * longest line length / (16 * tclk) = 1.2 * 63.5 / (16 * 0.07) = 68 = 0x44 0x44
gm_WriteRegByte(SYNC_TIP_CLAMP_TIME_OUT, 0x44);
// Louis 1103
//ADC_CLAMP_START Clamp start is programmed to 1 0X01
gm_WriteRegByte(ADC_H_CLAMPSTART, 0x01); // 0x01
//ADC_CLAMPWIDTH Clam Width is programmed to 2. 0X02
gm_WriteRegByte(ADC_H_CLAMPWIDTH, 0x04); // 0x02
//ADC_FAS_hi/lo constant to 0x040C 0x040C
gm_WriteRegByte(ADC_FAS1, MSB_CLMP);
//ADC_TEST_hi/lo constant to 0x0010 0x0010
gm_WriteRegByte(ADC_TEST1, 0x00);
gm_WriteRegByte(ADC_TEST2, DIS_RACLK | I_BIAS);
//ADC_MODULATION set to 0 before it perform the adc linearity calibration 0x00
// gm_WriteRegByte(ADC_MODULATION, 0x00),
gm_WriteRegByte(ADC_SYNC_LEVEL,((ADC_SYNC_L_H_THRSH_VAL << ADC_SYNC_L_H_SHIFT) | (ADC_SYNC_H_L_THRSH_VAL << ADC_SYNC_H_L_SHIFT)));
//Maximum Sampling BW
gm_WriteRegByte(ADC_B_PHASE,ADC_BW);
// Set CDAC_GN before performing ADC Linearity.
gm_WriteRegByte(MISSING_CODE_TEST, CDAC_GN);
/********************************************************************/
/* Initialize: DVI */
/********************************************************************/
gm_WriteRegByte(DVI_CTRL, (RTERM_MAN | ( RTERM_49Ohm << RTERM_SHIFT )));
gm_WriteRegByte(DVI_EQUALIZATION, 0x00 ); //set equalizer freq response to normal ( < 1m cable)
gm_WriteRegByte(DVI_CONFIG, PWRUP_STANDBY | MANPHASE_EN | RX_FREQ_HIGH ); //Stay in standby state
gm_WriteRegByte(DVI_PLL, DLPF | BW_4M | (0x02 << MS_SHIFT));
gm_WriteRegByte(DVI_DE, DE_THRESHOLD_64 | DE_SEL_ALL); // | (3 << PHASE_SEL_SHIFT)
gm_WriteRegByte(CLKMEAS_CONTROL, CLKMEAS_WIDTH_256 | CLKMEAS_SRC_DVI);
/********************************************************************/
/* Initialize: IP and IFM */
/********************************************************************/
//IP_CONTROL enable input capture 0x04
gm_WriteRegByte(IP_CONTROL, IP_RUN_EN | IP_SOURCE_RGB);
//IPH_ACT_START programmed with constant value 8
gm_WriteRegWord(IPH_ACT_START, IPHS_ActiveStart);
//IPV_ACT_START_ODD constant to 10
gm_WriteRegWord(IPV_ACT_START_ODD, IPVS_ActiveStart);
//IPV_ACT_START_EVEN constant to 10
gm_WriteRegWord(IPV_ACT_START_EVEN, IPVS_ActiveStart);
//SRC_VTOTAL panel typical Vtotal 806
gm_WriteRegWord(SRC_VTOTAL, 0);
//IP_FLAGLINE initial constant to 0x01 0x01
gm_WriteRegWord(IP_FLAGLINE, 1);
//CSYNC_CONTROL Automatically Detected for each SYNC type 0x4E
gm_WriteRegByte(CSYNC_CONTROL, HSRAW_DIS | CSYNC_SAMPLE4);
// Louis 1103
//gm_WriteRegByte(IFM_CTRL, INT_MODE_SEL | IFM_MEASEN | IFM_EN | INT_ODD_EN | AUTO_HOFFSET_EN | IFM_HOFFSETEN),
gm_WriteRegByte(IFM_CTRL, IFM_SRC_RGB | INT_MODE_SEL | IFM_MEASEN | IFM_EN | INT_ODD_EN | AUTO_HOFFSET_EN | IFM_HOFFSETEN);
//IFM_WATCHDOG, program with large enough values to cover C-sync modes
//which don't have Hsync pulses during the Vsync.
gm_WriteRegByte(IFM_WATCHDOG, 0x46);
//IFM_FIELD_CONTROL Fixed value. based on 14.3Mhz Tclk 0x20
gm_WriteRegByte(IFM_FIELD_CONTROL, 0x30);
//IFM_HLINE Fixed value to 0x0040 0x0040
gm_WriteRegWord(IFM_HLINE, 0x0040);
//IFM_CHANGE Fixed to Threshold of 8 0x24
//gm_WriteRegByte(IFM_CHANGE, IFM_CHG_THRESH_8 | (IFM_CHG_THRESH_8 << V_CHG_THRESH_SHIFT)),
// #PDR14327, Add DVI DE change threshold level (DE_CHG_THRESH) for DVI DE jitter issue (Default 0), Louis 010305
gm_WriteRegByte(IFM_CHANGE, IFM_CHG_THRESH_8 | (IFM_CHG_THRESH_8 << V_CHG_THRESH_SHIFT) | (SEL_DE_CHG_THRESH << DE_CHG_THRESH_SHIFT));
gm_WriteRegByte(IBD_CONTROL, (IBD_THRESH_32 << DET_THOLD_SHIFT) | (RGB_SEL_RGB << RGB_SEL_SHIFT));
gm_WriteRegByte(ALT_DISP_ADJ_LINES, Alt_DispLines);
/********************************************************************/
/* Initialize: FILTER */
/********************************************************************/
// set LCLK to 10% higher than maximum panal clock (dclk)
gm_WriteRegWord(LCLK_FREQ, ((LCLK_MHZ << 16) / RCLK_MHZ));
// Louis 1104
//gm_WriteRegByte(FILTER_CONTROL, LCLK_SEL | FILTER_MODE),
gm_WriteRegByte(FILTER_CONTROL, FILTER_MODE_VER_THREE_TAP | FILTER_MODE_HOR_THREE_TAP);
gm_WriteRegByte(HOR_INIT_PHASE, 0x0);
gm_WriteRegByte(VERT_INIT_PHASE, 0x8);
gm_WriteRegByte(HOR_ALT_PHASE, 0x0);
gm_WriteRegByte(VERT_ALT_PHASE, 0x0);
gm_WriteRegByte(DP_SYNC_ADJUST_CTRL, DP_ADJ_AUTO_EN);
// Louis 1104
gm_WriteRegByte(POST_LUT_DITHER_CTRL, 0xDE); // 0xDF), // Louis 1109
gm_WriteRegByte(DISP_LUT_DITHER_PRE_FIL, 0xC8); //0xCC), //0x88), // 0xCC), // 1125
gm_WriteRegByte(DISP_DITHER_ERR_CORECT, 0x8F); // 1109 0x8E), // Louis 1107
gm_WriteRegByte(DISP_DITHER_FIL_COEFF, 0x42);
/********************************************************************/
/* Initialize: COLOR */
/********************************************************************/
// 0401 Move to Panel segment
//#if (PanelDepth == 8)
// gm_WriteRegByte(MULT_DITHER_CTRL, (MULT_DITH_TRUNC | MULT_DITH_1FRAME)),
//#else
// gm_WriteRegByte(MULT_DITHER_CTRL, MULT_DITH_SPATIAL),
//#endif
// Panel parameter init has been moved to InitPanelParameters() above
// since panel parameters are now run time variables, and can not be
// initiaized with gm_WriteRegBlock routine.
gm_WriteRegByte(HOST_CONTROL, IPFORCE_UPDATE | DPFORCE_UPDATE);
}
//******************************************************************
// FUNCTION : gm_Print
// DESCRIPTION : If debugging using JTAG, then we don't want any
// UART activity since they share the same port pins.
// if DEBUG_JTAG is enabled, then this gm_Print function
// will override the GSEL gm_Print function and effectively
// stop all prints.
//******************************************************************
#if (DEBUG_JTAG == 1)
#pragma warn -par
void far gm_Print (const char far *Bp_Str, WORD W_Value)
{
return;
}
#pragma warn +par
#endif
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