📄 register_26xx.h
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// PATGEN_GRN (0x80C2)
#define BGND_GRN 0X0F
#define FGND_GRN 0XF0
// PATGEN_RED (0x80C3)
#define BGND_RED 0X0F
#define FGND_RED 0XF0
// IFM_CTRL (0x80CE)
#define IFM_EN BIT0
#define IFM_MEASEN BIT1
#define IFM_HOFFSETEN BIT2
#define IFM_SOURCE_SEL BIT4
#define INT_ODD_EN BIT5
#define AUTO_HOFFSET_EN BIT6
#define INT_MODE_SEL BIT7
#define IFM_SRC_DVI 0x00
#define IFM_SRC_RGB 0x10
// IFM_WATCHDOG (0x80CF)
#define IFM_H_WATCHDOG 0X0F
#define IFM_V_WATCHDOG 0XF0
// IFM_FIELD_CONTROL (0x80D0)
#define IFM_LOWER_ODD 0X0F
#define IFM_UPPER_ODD 0XF0
// IFM_CHANGE (0x80D1)
#define H_CHG_THRESH 0X07
#define V_CHG_THRESH 0X38
//#define DE_CHG_THRESH 0XC0 // Reserced, 0128
#define IFM_CHG_THRESH_0 0
#define IFM_CHG_THRESH_1 1
#define IFM_CHG_THRESH_2 2
#define IFM_CHG_THRESH_4 3
#define IFM_CHG_THRESH_8 4
#define IFM_CHG_THRESH_16 5
#define IFM_CHG_THRESH_32 6
#define IFM_CHG_THRESH_64 7
#define V_CHG_THRESH_SHIFT 3
// IBD_CONTROL (0x80DF)
#define DE_MEASURE_EN BIT0
#define IBD_WINDOW_EN BIT1
#define RGB_SEL 0X0C
#define DET_THOLD 0XF0
#define DET_THOLD_SHIFT 4
#define RGB_SEL_MASK 0x0C
#define RGB_SEL_SHIFT 2
#define RGB_SEL_RGB 0
#define RGB_SEL_R 1
#define RGB_SEL_G 2
#define RGB_SEL_B 3
#define IBD_THRESH_32 2
#define IBD_THRESH_128 8
// PIXGRAB_X_1 (0x80ED)
#define PIXGRAB_EN BIT4
// INST_AUTO_CTRL (0x80F8)
#define INST_AUTO_RUN BIT0
#define INST_AUTO_MODE BIT1
#define DIFF_CTRL 0X1C
#define INST_AUTO_CH_SEL 0XE0
// INST_AUTO_CTRL2 (0x80FB)
#define PHASE_EDGE_QUAL 0X03
#define EDGE_PROPORTION 0X0C
#define EDGE_PROPORTION_SHIFT 2
#define INST_AUTO_BUFFER_LIMIT_FLAG BIT4
#define INST_AUTO_DATA_ERROR BIT5
#define INST_AUTO_RSVR BIT6
#define INST_AUTO_STEALTH_EN BIT7
// SUMDIFF_MINMAX (0x8102)
// #define SUMDIFF_EN BIT0
// #define SUMDIFF_SEL 0X06
// CLKMEAS_CONTROL (0x810C)
#define CLKSRC_SEL 0X07
#define MEASURE_WIDTH 0X18
#define CLKMEAS_SRC_VIDEO 0x00
#define CLKMEAS_SRC_DVI 0x01
#define CLKMEAS_SRC_DDDS 0x02
#define CLKMEAS_SRC_SDDS 0x03
#define CLKMEAS_SRC_RCLK 0x04
#define CLKMEAS_WIDTH_256 0x18
// FILTER_CONTROL (0x8110)
#define HSHRINK_EN BIT0
#define VSHRINK_EN BIT1
#define LCLK_SEL BIT2
#define FILTER_MODE BIT3
#define SCALER_CLIP_EN BIT6
#define PHASE_ALT BIT7
// FILTER_COEFF_INDEX (0x8111)
#define FILTER_INDEX 0X3F
// VERT_INIT_PHASE (0x811F)
#define VERT_INIT_PHASE_MASK 0x1f
// FILTER_DITHER_CTRL (0x8113)
#define FILTER_DITH_SEL 0X03
#define FILTER_DITH_MOD 0X0C
// OSD_ENABLES (0x8128)
#define OSD_REC1_EN BIT0
#define OSD_REC2_EN BIT1
#define GL_OSD_EN BIT4
// OSD_CONTROL (0x8129)
#define OSDR1_BL_EN BIT0
#define OSDR2_BL_EN BIT1
#define FONT_MIRROR_EN BIT4
// OSD_BLEND_TABLE0 (0x812C)
#define BLEND_VAL0 0X0F
#define BLEND_VAL1 0XF0
// OSD_BLEND_TABLE1 (0x812D)
#define BLEND_VAL2 0X0F
#define BLEND_VAL3 0XF0
// OSD_BLEND_TABLE2 (0x812E)
#define BLEND_VAL4 0X0F
#define BLEND_VAL5 0XF0
// OSD_BLEND_TABLE3 (0x812F)
#define BLEND_VAL6 0X0F
#define BLEND_VAL7 0XF0
// OSD_R1_FONT_SIZE (0x8139)
#define OSD_R1_FONTX 0X07
#define OSD_R1_FONTY 0XF0
// OSD_R1_CHARMAP_CTRL (0x813A)
#define OSD_R1_HSPACE 0X03
#define OSD_R1_VSPACE 0X1C
#define OSD_R1_ROM_FONT_EN BIT5
#define OSD_R1_HSTRETCH BIT6
#define OSD_R1_VSTRETCH BIT7
// OSD_R1_WIN_EN (0x813B)
#define OSD_R1_WIN1_EN BIT0
#define OSD_R1_WIN2_EN BIT1
#define OSD_R1_WIN3_EN BIT2
#define OSD_R1_WIN4_EN BIT3
// OSD_R1_WIN_INDEX0 (0x813C)
#define OSD_R1_WINDX_CW1 0X0F
#define OSD_R1_WINDX_CW2 0XF0
// OSD_R1_WIN_INDEX1 (0x813D)
#define OSD_R1_WINDX_CW3 0X0F
#define OSD_R1_WINDX_CW4 0XF0
// OSD_R2_FONT_SIZE (0x8173)
#define OSD_R2_FONTX 0X07
#define OSD_R2_FONTY 0XF0
// OSD_R2_CHARMAP_CTRL (0x8174)
#define OSD_R2_HSPACE 0X03
#define OSD_R2_VSPACE 0X1C
#define OSD_R2_ROM_FONT_EN BIT5
#define OSD_R2_HSTRETCH BIT6
#define OSD_R2_VSTRETCH BIT7
// OSD_R2_WIN_EN (0x8175)
#define OSD_R2_WIN1_EN BIT0
#define OSD_R2_WIN2_EN BIT1
#define OSD_R2_WIN3_EN BIT2
#define OSD_R2_WIN4_EN BIT3
// OSD_R2_WIN_INDEX0 (0x8176)
#define OSD_R2_WINDX_CW1 0X0F
#define OSD_R2_WINDX_CW2 0XF0
// OSD_R2_WIN_INDEX1 (0x8177)
#define OSD_R2_WINDX_CW3 0X0F
#define OSD_R2_WINDX_CW4 0XF0
// DDS_CONTROL (0x81A8)
#define FORCE_SDDS_OPLOOP BIT0
#define FORCE_DDDS_OPLOOP BIT1
#define SDDS_ENABLE BIT2
#define DDDS_ENABLE BIT3
#define ACLK2_ENABLE BIT4
#define FCLK_ENABLE BIT5
#define LCLK_ENABLE BIT6
// DDS_STATUS (0x81A9)
#define SDDS_OPEN_LOOP BIT0
#define DDDS_OPEN_LOOP BIT1
// SDDS_CONTROL (0x81AA)
#define NO_HSYNC_CORR BIT1
#define K_MAIN_MASK 0X1C
#define K_DIFF_MASK 0XE0
#define K_MAIN 0X07
#define K_DIFF 0X04
#define K_MAIN_SHIFT 2
#define K_DIFF_SHIFT 5
// SAMPLING_PHASE_DELAY (0x81B2)
#define PHASE_DELAY 0X3F
// SDDS_FREQUENCY_DELTA_THRESH (0x81B4)
#define SDDS_FREQ_THRESH 0XFF
// SDDS_TRACKING_ERR (0x81B5)
#define SDDS_TRACK_ERR 0XFF
// SDDS_TEST_CNTRL1 (0x81BB)
#define HSYNC_WINDOW 0X3F
#define HS_IPCLK_MANUAL BIT6
#define SDDS_TEST_RSVR1 BIT7
// DDDS_CONTROL (0x81C2)
#define SPREAD_SP_EN BIT1
#define D_K_MAIN 0X1C
#define D_K_DIFF 0XE0
#define D_K_MAIN_SHIFT 2
#define D_K_DIFF_SHIFT 5
#define D_K_MAIN_MASK 0x1C
#define D_K_DIFF_MASK 0xE0
#define SPREAD_SP_EN_SHIFT 1
// DDDS_FREQUENCY_DELTA_THRESH (0x81D0)
#define DDDS_FREQ_THRESH 0XFF
// DDDS_TRACKING_ERR (0x81D1)
#define DDDS_TRACK_ERR 0XFF
// DDDS_ESM_CTRL (0x81D6)
#define SP_AMPLITUDE 0X03
#define SP_PERIOD 0XFC
// OP_ENABLE (0x81E0)
#define POWER_SEQ_EN BIT0
#define DCLK_EN BIT1
#define DCNTL_EN BIT2
#define DDATA_EN BIT3
#define POWER_SEQ_TICK_DIV2 BIT4
#define OP_RSVR 0XE0
// DISPLAY_CONTROL (0x81E2)
#define FORCE_PROGRESSINVE BIT0
#define FORCE_BKGND BIT2
#define OSD_SYNC_START_OPT⌨️ 快捷键说明
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