register_26xx.h

GM5621原代码

	#define SPI_ATMEL_ROM                         BIT3

	// SPI_CACHE_CTRL                             (0x802E)
	#define SPI_CACHE_EN                          BIT0
	#define SPI_FAST_READ_EN                      BIT1

	// PWM0_CONFIG                                (0x8030)
	#define PWM0_GPO_EN                           BIT0
	#define PWM0_CLKSEL                           BIT1
	#define PWM0_PRESCALE                         0X0C
	#define PWM0_VSRESET                          BIT4
	#define PWM0_10BIT_PULSE                      BIT5
	#define PWM0_TCLK_DIV                         BIT6

	// PWM1_CONFIG                                (0x8033)
	#define PWM1_GPIO_EN                          BIT0
	#define PWM1_CLKSEL                           BIT1
	#define PWM1_PRESCALE                         0X0C
	#define PWM1_VSRESET                          BIT4
	#define PWM1_10BIT_PULSE                      BIT5
	#define PWM1_TCLK_DIV                         BIT6

	// GPIO_DIRCTRL1                              (0x803C)
	#define GPIO0_IO                              BIT0
	#define GPIO1_IO                              BIT1
	#define GPIO2_IO                              BIT2
	#define GPIO3_IO                              BIT3
	#define GPIO4_IO                              BIT4
	#define GPIO5_IO                              BIT5
	#define GPIO6_IO                              BIT6

	// GPO_OPENDRAIN_EN1                          (0x803D)
	#define GPIO0_OD                              BIT0
	#define GPIO1_OD                              BIT1
	#define GPIO2_OD                              BIT2
	#define GPIO3_OD                              BIT3
	#define GPIO4_OD                              BIT4
	#define GPIO5_OD                              BIT5
	#define GPIO6_OD                              BIT6

	// GPINPUT1                                   (0x803E)
	#define GPIO0_IN                              BIT0
	#define GPIO1_IN                              BIT1
	#define GPIO2_IN                              BIT2
	#define GPIO3_IN                              BIT3
	#define GPIO4_IN                              BIT4
	#define GPIO5_IN                              BIT5
	#define GPIO6_IN                              BIT6

	// GPOUTPUT1                                  (0x803F)
	#define GPIO0_OUT                             BIT0
	#define GPIO1_OUT                             BIT1
	#define GPIO2_OUT                             BIT2
	#define GPIO3_OUT                             BIT3
	#define GPIO4_OUT                             BIT4
	#define GPIO5_OUT                             BIT5
	#define GPIO6_OUT                             BIT6

	// GPO_OUTPUT                                 (0x8040)
	#define GPO0_OUT                              BIT0
	#define GPO1_OUT                              BIT1
	#define GPO2_OUT                              BIT2
	#define GPO3_OUT                              BIT3
	#define GPO4_OUT                              BIT4
	#define GPO5_OUT                              BIT5

	// GPO_OPENDRAIN_EN                           (0x8041)
	#define GPO0_OD                               BIT0
	#define GPO1_OD                               BIT1
	#define GPO2_OD                               BIT2
	#define GPO3_OD                               BIT3
	#define GPO4_OD                               BIT4
	#define GPO5_OD                               BIT5

	// GPINPUT                                    (0x8042)
	#define GPO2_IN                               BIT2

	// LOW_BW_ADC_CTRL                            (0x8048)
	#define LBADC_START_CONV                      BIT0
	#define LBADC_EN                              BIT1
	#define LBADC_INPUT_SEL                       0X0C
	#define LBADC_INPUT_SEL_SHIFT                 2
	#define LBADC_CLKDIV                          0X60

	// LOW_BW_ADC_RESULT                          (0x8049)
	#define LBADC_RD_DATA                         0XFF

	// LOW_BW_ADC_STATUS                          (0x804A)
	#define LBADC_CONV_DONE                       BIT0
	
	//Power_Status
	#define BROWN_OUT_30			0
	#define BROWN_OUT_27			1

   // AOC_CTRL                                   (0x8050)
   #define AOC_EN                                BIT0
   #define AOC_DONT_UPDATE                       BIT1

	// phyang 01/26/06: 9-bit Offset1.
	// ADC_RED_GRN_OFFSE1_LSB		(0x805E)
	#define RED_OFFSET1_LSB_MASK	0x07
	#define RED_OFFSET1_LSB_SHIFT	0
	#define GRN_OFFSET1_LSB_MASK	0x70
	#define GRN_OFFSET1_LSB_SHIFT	4
    	
	// ADC_BLU_OFFSET1_LSB			(0x805F)
	#define BLU_OFFSET1_LSB_MASK	0x07
	#define BLU_OFFSET1_LSB_SHIFT	0

	// ADC_CONTROL                                (0x8060)
	#define SOG_SENS                              0X03
	#define SOG_EN                                BIT2
	#define AC_COUPLE_EN                          BIT3
	#define CLAMP_EN                              BIT4
	#define SYNCTIP_EN                            BIT5
	#define ADC_ENABLE                            BIT6
	#define PD_ADC                                BIT7
	#define SOG_SENS_MASK                         0x03
	#define SOG_SENS_SHIFT                        0

	// ADC_SYNC_LEVEL                             (0x8063)
	#define ADC_SYNC_L_H_THRSH                    BIT0
	#define ADC_SYNC_H_L_THRSH                    BIT2
	#define ADC_SYNC_L_H_SHIFT                    0
	#define ADC_SYNC_H_L_SHIFT                    2

	// ADC_FAS1                                   (0x8064)
	#define AMP1_OSADJ                            BIT4
	#define ADC_REFADJ                            0X03
	#define MSB_CLMP                              BIT2
	#define LOCK_MSB                              BIT3
	#define ACLK_INV                              BIT5
	#define PDLL                                  0XC0

	// ADC_FAS2                                   (0x8065)
    #define I_OTHA                                BIT0
    #define I_ITHA                                BIT1
    #define VBG_IB                                BIT4
    #define I_MSB                                 BIT5
    #define I_LSB                                 BIT6
    #define DIS_DERC                              BIT7

	// ADC_TEST1                                  (0x8066)
   #define ADC_EQ										 	 0x7
   #define THREE_BIT_EQ

	// ADC_TEST2                                  (0x8067)
	#define I_BIAS                                0X03
	#define FS_ADJ1                               BIT2
	#define DIS_LSBCLK                            BIT3
	#define DIS_RACLK                             BIT4
	#define RST_DLL                               BIT5
	#define EXT_ACLK                              BIT6
	#define SOG_PULLUP                            BIT7

	// ADC_FLAGS                                  (0x806B)
	#define R_OVFL                                BIT0
	#define R_UNDFL                               BIT1
	#define G_OVFL                                BIT2
	#define G_UNDFL                               BIT3
	#define B_OVFL                                BIT4
	#define B_UNDFL                               BIT5

	// ADC_TESTDAC                                (0x8078)
	#define RED_ST                                BIT0
	#define GRN_ST                                BIT1
	#define BLU_ST                                BIT2
	#define SOG_RST                               BIT3

	// ADC_DAC_DATA                               (0x8079)
	#define DAC_ST                                0XFF

	// ADC_MODULATION                             (0x807A)
	#define LINEMODU_EN                           BIT1
	#define FRAMEMODU_EN                          BIT2
	#define COMP_VID_EN                           BIT3
	#define CONT_CAL                              BIT5
	#define CAL_TRIG                              BIT6
	#define RSVR_ADC1                             BIT7


	// MISSING_CODE_TEST                          (0x807B)
	#define RST_CAL                               BIT1
	#define ST_DAC                                BIT6
	#define EN_CAL                                BIT0
	#define CLR_CAL                               BIT2
	#define CSET_ADD                              BIT3
	#define CSET_SUB                              BIT4
	#define SLRMP                                 BIT5
	#define STDAC                                 BIT6
	#define CDAC_GN                               BIT7

	// ADC_RG_PHASE                               (0x807C)
	#define ADC_PH_R_DELAY                        0X07
	#define ADC_PH_G_DELAY                        0X70

	// ADC_B_PHASE                                (0x807D)
	#define ADC_PH_B_DELAY                        0X07
	#define ADC_BW                                0XF0
   #define FOUR_BIT_BW

	// SYNC_TIP_CLAMP_END                         (0x807E)
	#define ADC_TIP_CLAMP_END                     0XFF

	// SYNC_TIP_CLAMP_TIME_OUT                    (0x807F)
	#define ADC_TIP_CLAMP_TIMEOUT                 0XFF


	// IP_CONTROL                                 (0x80A0)
	#define IP_SOURCE_SEL                         BIT1
	#define IP_RUN_EN                             BIT2
	#define IP_INTERLACE_EN                       BIT4
	#define IBD_HS_DELAY                          BIT5
	//#define DVI_HSVS_REGEN                        BIT6		// Reserced, 0128
	#define VSYNC_DIV2_EN                         BIT7
	#define IP_SOURCE_RGB                         0x00
	#define IP_SOURCE_DVI                         0x02



	// IP_POLARITY                                (0x80A1)
	#define IPCLK_INV                             BIT0
	#define IPVS_INV                              BIT1
	#define IPHS_INV                              BIT2
	#define IPODD_INV                             BIT3

	// CSYNC_CONTROL                              (0x80A3)
	#define CSYNC_EN                              BIT0
	#define ADC_CLAMP_REF                         BIT1
	#define CSYNC_SAMPLE                          0X0C
	#define HSREGEN_SLOW_LOCK                     BIT4
	#define CSYNC_VS_MASK_EN                      BIT5
	#define HSRAW_DIS                             BIT6
	#define IFM_HSYNC_SEL                         BIT7
	#define CSYNC_SAMPLE_MASK                     0X0C
	#define CSYNC_SAMPLE1				          	  0x00
	#define CSYNC_SAMPLE2				          	  0x04
	#define CSYNC_SAMPLE3				          	  0x08
	#define CSYNC_SAMPLE4				          	  0x0C



	// PATGEN_CONTROL                             (0x80C0)
	#define PAT_SEL                               0X1F
	#define TPG_EN                                BIT5
	#define PATTERN_SET                           0XC0

	// PATGEN_BLUE                                (0x80C1)
	#define BGND_BLUE                             0X0F
	#define FGND_BLUE                             0XF0