📄 register_26xx.h
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#define DST_FREE_RUN_CNTRL 0x8218 //33304 ()
#define RED_CONTRAST_0 0x8220 //33312 ()
#define RED_CONTRAST_1 0x8221 //33313 ()
#define RED_CONTRAST RED_CONTRAST_0
#define GREEN_CONTRAST_0 0x8222 //33314 ()
#define GREEN_CONTRAST_1 0x8223 //33315 ()
#define GREEN_CONTRAST GREEN_CONTRAST_0
#define BLUE_CONTRAST_0 0x8224 //33316 ()
#define BLUE_CONTRAST_1 0x8225 //33317 ()
#define BLUE_CONTRAST BLUE_CONTRAST_0
#define RED_BRIGHTNESS 0x8226 //33318 ()
#define GREEN_BRIGHTNESS 0x8227 //33319 ()
#define BLUE_BRIGHTNESS 0x8228 //33320 ()
#define MULT_DITHER_CTRL 0x8229 //33321 ()
#define DISP_LUT_CTRL 0x8270 //33392 ()
#define POST_LUT_DITHER_CTRL 0x8271 //33393 ()
#define ADC_FILTER_CONFIG 0x8278
#define ADC_FILTER_DELTA_THRESH 0x8279
#define ADC_FILTER_LOW_THRESH 0x827A
#define ADC_FILTER_HIGH_THRESH 0x827B
#define VIRTUAL_EDID_CONTROL 0x8290 //33424 ()
#define VIRTUAL_EDID_DATA 0x8291 //33425 ()
#define VIRTUAL_EDID_ADDRESS 0x8292 //33426 ()
#define VIRTUAL_EDID_STATUS 0x8293 //33427 ()
#define MEM_TEST_SIGNATURE_CTRL 0x8294 //33428 ()
#define ROM_TEST_SIG_0 0x8296 //33430 ()
#define ROM_TEST_SIG_1 0x8297 //33431 ()
#define ROM_TEST_SIG_2 0x8298 //33432 ()
#define MEM_TEST_PATTERN 0x829A
#define MEM_TEST_ENABLE 0x829B
#define MEM_TEST_RESULT 0x829C
#define USER_TEST_VALUE_0 0x829E
#define USER_TEST_VALUE_1 0x829F
#define USER_TEST_VALUE USER_TEST_VALUE_0
#define ADC_AUTST_LIN_DATA 0x82A9
#define ADC_AUTST_STATUS 0x82AA
#define ADC_AUTST_CTRL 0x82AB
#define ADC_AUTST_SEL 0x82AC
#define ADC_AUTST_HIT 0x82AD
#define CCF_TESTREG 0x82AE //33454 ()
#define RPLL_TEST_CONTROL 0x82AF
#define DDC2B_CTRL1 0x82B8 //33464 ()
#define DDC2B_CTRL2 0x82B9 //33465 ()
#define DDC2B_STATUS 0x82BA //33466 ()
#define DDC2B_ADDR 0x82BB //33467 ()
#define DDC2B_CLOCK_STATUS 0x82BC //33468 ()
#define DDC2B_DATA 0x82BE //33470 ()
#define RSDS_LVDS_POWER 0x82C0 //33472 ()
#define RSDS_LVDS_DATA_CTRL 0x82C1 //33473 ()
#define LVDS_PLL_CTRL 0x82C2 //33474 ()
#define RSDS_LVDS_MISC1_CTRL 0x82C3 //33475 ()
#define RSDS_LVDS_MISC2_CTRL 0x82C4 //33476 ()
#define CLOCK_SIGNAL_DELAY 0x82C5 //33477 ()
#define RSDS_LVDS_TEST_CTRL 0x82C6 //33478 ()
#define LVDS_TEST_DATA 0x82C7 //33479 ()
#define LVDS_CLK_DATA 0x82C8 //33480 ()
#define BP0_CTRL 0x8300 //33536 ()
#define BP0_OCM_ADDR_0 0x8302 //33538 ()
#define BP0_OCM_ADDR_1 0x8303 //33539 ()
#define BP0_SUB_ADDR_0 0x8304 //33540 ()
#define BP0_SUB_ADDR_1 0x8305 //33541 ()
#define BP1_CTRL 0x8306 //33542 ()
#define BP1_OCM_ADDR_0 0x8308 //33544 ()
#define BP1_OCM_ADDR_1 0x8309 //33545 ()
#define BP1_SUB_ADDR_0 0x830A //33546 ()
#define BP1_SUB_ADDR_1 0x830B //33547 ()
#define BP2_CTRL 0x830C //33548 ()
#define BP2_OCM_ADDR_0 0x830E //33550 ()
#define BP2_OCM_ADDR_1 0x830F //33551 ()
#define BP2_SUB_ADDR_0 0x8310 //33552 ()
#define BP2_SUB_ADDR_1 0x8311 //33553 ()
#define BP3_CTRL 0x8312 //33554 ()
#define BP3_OCM_ADDR_0 0x8314 //33556 ()
#define BP3_OCM_ADDR_1 0x8315 //33557 ()
#define BP3_SUB_ADDR_0 0x8316 //33558 ()
#define BP3_SUB_ADDR_1 0x8317 //33559 ()
/****************************************************************************/
/* B I T D E F I N I T I O N S */
/****************************************************************************/
// HOST_CONTROL (0x8000)
#define SOFT_RESET BIT0
#define IPSYNC_UPDATE BIT1
#define DPSYNC_UPDATE BIT2
#define IPFORCE_UPDATE BIT3
#define DPFORCE_UPDATE BIT4
#define SYNC_UPDATE (IPSYNC_UPDATE | DPSYNC_UPDATE)
#define FORCE_UPDATE (IPFORCE_UPDATE | DPFORCE_UPDATE)
// CLOCK_CONFIG (0x8003)
#define IP_CLKSEL 0X03
//#define IP_CLK_DVI 0x00 // No DVI, Reserced, 0128
#define IP_CLK_EXT_DIV2 0x01
#define IP_CLK_RGB 0x02
#define IP_CLK_EXT_DIV 0x03
#define IFM_CLKSEL BIT2
#define IFM_CLK_TCLK 0x00
#define ACLK_SEL BIT3
#define ACLK_SDDS 0x00
#define OCM_CLKSEL 0X30
#define OCM_CLK_TCLK 0x00
#define OCM_CLK_F_DDS BIT4
#define OCM_CLK_GPIO3 BIT5
#define OCM_CLKSEL 0X30
#define DP_CLKSEL 0XC0
#define DP_CLK_IP_CLK_INV 0x00
#define DP_CLK_DCLK BIT6
#define DP_CLK_GPIO1 BIT7
#define DP_CLK_IPCLK 0xC0
// BYPASS (0x8006)
#define POWER_DOWN BIT0
#define CAPTURE_ONLY BIT1
//#define TCON_LB_BYPASS BIT2 // Reserced, 0128
#define SCALER_PASSTHRU BIT3
#define P2S_BYPASS BIT4
#define TCON_SIGNALS_OFF BIT5
#define RSVR_BYPASS 0XC0
// IRQ_CONFIG (0x800B)
#define GPIO_IRQ_OUT_EN BIT0
#define IRQn_LATCHED BIT1
#define IRQn_ACTHIGH BIT2
// IFM_OCMMASK (0x800C)
#define OCM_NO_HS BIT0
#define OCM_NO_VS BIT1
#define OCM_HS_PERIOD_ERR BIT2
#define OCM_VS_PERIOD_ERR BIT3
#define OCM_DVI_DE_WIDTH_ERR BIT4
#define IP_ODD BIT6
#define OCM_INTLC_ERR BIT7
// INPUT_OCMMASK (0x800D)
#define OCM_IP_ACTIVE BIT0
#define OCM_IP_VBLANK BIT1
#define OCM_IP_LINEFLAG BIT2
#define IP_VS_FLAG BIT3
#define OCM_LBW_ADC_RDY BIT4
#define DDC2Bi_MASK BIT6
#define SPI_IRQ BIT7
// MISC_OCMMASK (0x800E)
#define OCM_D_ACTIVE BIT0
#define OCM_D_VBLANK BIT1
#define OCM_D_LINEFLAG BIT2
#define D_VS BIT3
#define OCM_AFR_ACTIVE BIT4
#define CLK_EVENT BIT6
#define BP_IRQ BIT7
// SYSTEM_STATUS (0x800F)
#define IP_ODD_STATUS BIT2
#define IFM_IRQ BIT3
#define INPUT_IRQ BIT4
#define DISPLAY_IRQ BIT5
#define CLOCK_IRQ BIT6
// IFM_STATUS (0x8010)
#define NO_HS BIT0
#define NO_VS BIT1
#define HS_PERIOD_ERR BIT2
#define VS_PERIOD_ERR BIT3
#define DVI_DE_WIDTH_ERR BIT4
#define BP_IRQ_FLAG BIT5
#define VS_HS_CLOSE_ERR_FLAG BIT6
#define INTLC_ERR BIT7
// INPUT_STATUS (0x8011)
#define IP_ACTIVE BIT0
#define IP_VBLANK BIT1
#define IP_LINEFLAG BIT2
#define INPUT_VS BIT3
#define LBW_ADC_RDY BIT4
#define DDC2BI_IRQ BIT6
#define SPI_EXCH_FLAG BIT7
// DISPLAY_STATUS (0x8012)
#define D_ACTIVE BIT0
#define D_VBLANK BIT1
#define D_LINEFLAG BIT2
#define D_VS_FLAG BIT3
#define D_VS_LEVEL BIT4
#define D_VACTIVE BIT5
#define AFR_ACTIVE_FLAG BIT6
#define AFR_ACTIVE BIT6
#define BUFFER_OVERRUN BIT7
// CLOCK_STATUS (0x8013)
#define SRC_NOCLK BIT0
#define SRC_CLKERR BIT1
#define SDDS_OPENLOOP BIT2
#define DDDS_OPENLOOP BIT3
#define CLKMEAS_OFLOW BIT4
#define SRC_NOCLK BIT0
// MISC_STATUS (0x8014)
#define IP_VS BIT0
#define IP_VACTIVE BIT1
#define ADC_CAL BIT2
// RCLK_CONFIG (0x8016)
#define RCLK_POWER_DN BIT3
#define RCLK_RESET BIT4
// RCLK_FREQUENCY (0x8017)
#define RCLK_N 0X1F
#define RCLK_M 0X60
// RCLK_PLL (0x8018)
#define RCLK_BW_4M BIT0
#define RCLK_BW_H BIT1
#define RCLK_BW_TRACK BIT2
#define SEL_CLK2 BIT3
#define AGCON BIT5
#define OSCI BIT6
// OCM_BUS_CONTROL (0x8020)
#define ENABLE_WDT BIT0
#define EN_WDT_INTERRUPT BIT1
#define OCM_RAM_CTRL 0X0C
// OCM_BUS_WDT_INIT (0x8022)
#define OCM_WDT_INIT 0XFF
// OCM_BUS_WDT_STATUS (0x8023)
#define TRANSACTION_ERR BIT0
// OCM_CONTROL (0x8027)
#define OCM_RESET BIT0
#define OCM_UART_EN BIT1
#define OCM_UART_PIN_SEL BIT2
#define INT_ROM_EN BIT4
// SPI_CONTROL (0x802A)
#define SPI_CPHA BIT0
#define SPI_CLK_INV BIT1
#define SPI_BYTE_EX BIT2
#define SPI_PROGRAM_EN BIT3
#define SPI_CLK_SEL 0X70
#define FLASH_CHIP_SEL BIT7
// SPI_STATUS (0x802B)
#define SPI_EXCH_ACTIVE BIT0
#define SPI_WRITE_ERROR BIT1
#define SPI_BUSY BIT2
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