📄 register_56xx.h
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// ADC_TESTDAC (0x8078)
#define RED_ST BIT0
#define GRN_ST BIT1
#define BLU_ST BIT2
#define SOG_RST BIT3
// ADC_DAC_DATA (0x8079)
#define DAC_ST 0XFF
// ADC_MODULATION (0x807A)
#define LINEMODU_EN BIT1
#define FRAMEMODU_EN BIT2
#define COMP_VID_EN BIT3
#define CONT_CAL BIT5
#define CAL_TRIG BIT6
#define RSVR_ADC1 BIT7
// MISSING_CODE_TEST (0x807B)
#define RST_CAL BIT1
#define ST_DAC BIT6
#define EN_CAL BIT0
#define CLR_CAL BIT2
#define CSET_ADD BIT3
#define CSET_SUB BIT4
#define SLRMP BIT5
#define STDAC BIT6
#define CDAC_GN BIT7
// ADC_RG_PHASE (0x807C)
#define ADC_PH_R_DELAY 0X07
#define ADC_PH_G_DELAY 0X70
// ADC_B_PHASE (0x807D)
#define ADC_PH_B_DELAY 0X07
#define ADC_BW 0XF0
#define FOUR_BIT_BW
// SYNC_TIP_CLAMP_END (0x807E)
#define ADC_TIP_CLAMP_END 0XFF
// SYNC_TIP_CLAMP_TIME_OUT (0x807F)
#define ADC_TIP_CLAMP_TIMEOUT 0XFF
// DVI_CTRL (0x8080)
#define EN_CALRTERM BIT1
#define RTERM_MAN BIT2
#define RTERM 0X78
#define RST_FF BIT7
#define RTERM_49Ohm 0x08
#define RTERM_SHIFT 3
// DVI_EQUALIZATION (0x8081)
#define DVI_EQ 0X0F
#define EQ_GAIN BIT4
#define DIS_EQ_OS BIT5
#define BW_TRACKING 0XC0
// DVI_CONFIG (0x8082)
#define PWRUP_CTRL 0X03
#define RX_FREQ_SEL 0X0C
#define CH2IN_CLKDELAY 0X70
#define PWRUP_CTRL 0X03
#define PWRUP_OFF 0x00
#define PWRUP_STANDBY 0x01
#define PWRUP_ACTIVE 0x03
#define RX_FREQ_SEL 0X0C
#define RX_FREQ_SEL_SHIFT 2
#define RX_FREQ_LOW 0x00
#define RX_FREQ_MED 0x04
#define RX_FREQ_HIGH 0x08
#define CH2IN_CLKDELAY 0X70
// DVI_DE (0x8083)
#define DE_REGEN_DIS BIT0
#define DE_THRESHOLD 0X06
#define DE_SELECT 0X18
#define DE_THRESHOLD_16 0x00
#define DE_THRESHOLD_32 0x02
#define DE_THRESHOLD_64 0x04
#define DE_THRESHOLD_128 0x06
#define DE_SEL_CH0 0x00
#define DE_SEL_CH1 0x08
#define DE_SEL_CH2 0x10
#define DE_SEL_ALL 0x18
// DVI_PLL (0x8084)
#define DLPF BIT0
#define BW_4M BIT1
#define MS 0X0C
#define NS 0X30
#define BW_HALF BIT6
#define BW_TRACK BIT7
#define MS_SHIFT 2
#define NS_SHIFT 4
// DVI_MISC (0x8088)
#define DE_WIDTH_CLAMP_EN BIT0
#define SWAP_CH0_CH2 BIT3
#define DVI_RSVR 0XF0
// IP_CONTROL (0x80A0)
#define IP_SOURCE_SEL BIT1
#define IP_RUN_EN BIT2
#define IP_INTERLACE_EN BIT4
#define IBD_HS_DELAY BIT5
#define DVI_HSVS_REGEN BIT6
#define VSYNC_DIV2_EN BIT7
#define IP_SOURCE_RGB 0x00
#define IP_SOURCE_DVI 0x02
// IP_POLARITY (0x80A1)
#define IPCLK_INV BIT0
#define IPVS_INV BIT1
#define IPHS_INV BIT2
#define IPODD_INV BIT3
// CSYNC_CONTROL (0x80A3)
#define CSYNC_EN BIT0
#define ADC_CLAMP_REF BIT1
#define CSYNC_SAMPLE 0X0C
#define HSREGEN_SLOW_LOCK BIT4
#define CSYNC_VS_MASK_EN BIT5
#define HSRAW_DIS BIT6
#define IFM_HSYNC_SEL BIT7
#define CSYNC_SAMPLE_MASK 0X0C
#define CSYNC_SAMPLE1 0x00
#define CSYNC_SAMPLE2 0x04
#define CSYNC_SAMPLE3 0x08
#define CSYNC_SAMPLE4 0x0C
// PATGEN_CONTROL (0x80C0)
#define PAT_SEL 0X1F
#define TPG_EN BIT5
#define PATTERN_SET 0XC0
// PATGEN_BLUE (0x80C1)
#define BGND_BLUE 0X0F
#define FGND_BLUE 0XF0
// PATGEN_GRN (0x80C2)
#define BGND_GRN 0X0F
#define FGND_GRN 0XF0
// PATGEN_RED (0x80C3)
#define BGND_RED 0X0F
#define FGND_RED 0XF0
// IFM_CTRL (0x80CE)
#define IFM_EN BIT0
#define IFM_MEASEN BIT1
#define IFM_HOFFSETEN BIT2
#define IFM_SOURCE_SEL BIT4
#define INT_ODD_EN BIT5
#define AUTO_HOFFSET_EN BIT6
#define INT_MODE_SEL BIT7
#define IFM_SRC_DVI 0x00
#define IFM_SRC_RGB 0x10
// IFM_WATCHDOG (0x80CF)
#define IFM_H_WATCHDOG 0X0F
#define IFM_V_WATCHDOG 0XF0
// IFM_FIELD_CONTROL (0x80D0)
#define IFM_LOWER_ODD 0X0F
#define IFM_UPPER_ODD 0XF0
// IFM_CHANGE (0x80D1)
#define H_CHG_THRESH 0X07
#define V_CHG_THRESH 0X38
#define DE_CHG_THRESH 0XC0
#define IFM_CHG_THRESH_0 0
#define IFM_CHG_THRESH_1 1
#define IFM_CHG_THRESH_2 2
#define IFM_CHG_THRESH_4 3
#define IFM_CHG_THRESH_8 4
#define IFM_CHG_THRESH_16 5
#define IFM_CHG_THRESH_32 6
#define IFM_CHG_THRESH_64 7
#define V_CHG_THRESH_SHIFT 3
// #PDR14327, Add DVI DE change threshold level (DE_CHG_THRESH) for DVI DE jitter issue, Louis 010305
#define DE_CHG_THRESH_0 0
#define DE_CHG_THRESH_4 1
#define DE_CHG_THRESH_16 2
#define DE_CHG_THRESH_64 3
#define DE_CHG_THRESH_SHIFT 6
// IBD_CONTROL (0x80DF)
#define DE_MEASURE_EN BIT0
#define IBD_WINDOW_EN BIT1
#define RGB_SEL 0X0C
#define DET_THOLD 0XF0
#define DET_THOLD_SHIFT 4
#define RGB_SEL_MASK 0x0C
#define RGB_SEL_SHIFT 2
#define RGB_SEL_RGB 0
#define RGB_SEL_R 1
#define RGB_SEL_G 2
#define RGB_SEL_B 3
#define IBD_THRESH_32 2
#define IBD_THRESH_128 8
// PIXGRAB_X_1 (0x80ED)
#define PIXGRAB_EN BIT4
// INST_AUTO_CTRL (0x80F8)
#define INST_AUTO_RUN BIT0
#define INST_AUTO_MODE BIT1
#define DIFF_CTRL 0X1C
#define INST_AUTO_CH_SEL 0XE0
// INST_AUTO_CTRL2 (0x80FB)
#define PHASE_EDGE_QUAL 0X03
#define EDGE_PROPORTION 0X0C
#define EDGE_PROPORTION_SHIFT 2
#define INST_AUTO_BUFFER_LIMIT_FLAG BIT4
#define INST_AUTO_DATA_ERROR BIT5
#define INST_AUTO_RSVR BIT6
#define INST_AUTO_STEALTH_EN BIT7
// SUMDIFF_MINMAX (0x8102)
// #define SUMDIFF_EN BIT0
// #define SUMDIFF_SEL 0X06
// CLKMEAS_CONTROL (0x810C)
#define CLKSRC_SEL 0X07
#define MEASURE_WIDTH 0X18
#define CLKMEAS_SRC_VIDEO 0x00
#define CLKMEAS_SRC_DVI 0x01
#define CLKMEAS_SRC_DDDS 0x02
#define CLKMEAS_SRC_SDDS 0x03
#define CLKMEAS_SRC_RCLK 0x04
#define CLKM⌨️ 快捷键说明
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