📄 register_56xx.h
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#define DV_ACTIV_START_1 0x81FB //33275 ()
#define DV_ACTIV_START DV_ACTIV_START_0
#define DV_ACTIV_LENGTH_0 0x81FC //33276 ()
#define DV_ACTIV_LENGTH_1 0x81FD //33277 ()
#define DV_ACTIV_LENGTH DV_ACTIV_LENGTH_0
#define DV_BKGND_END_0 0x8202 //33282 ()
#define DV_BKGND_END_1 0x8203 //33283 ()
#define DV_BKGND_END DV_BKGND_END_0
#define BKGND_RED 0x8204 //33284 ()
#define BKGND_GRN 0x8205 //33285 ()
#define BKGND_BLU 0x8206 //33286 ()
#define DP_FLAGLINE_0 0x8208 //33288 ()
#define DP_FLAGLINE_1 0x8209 //33289 ()
#define DP_FLAGLINE DP_FLAGLINE_0
#define DV_POSITION_0 0x820A //33290 ()
#define DV_POSITION_1 0x820B //33291 ()
#define DV_POSITION DV_POSITION_0
#define PANEL_POWER_STATUS 0x820C //33292 ()
#define PANEL_PWR_UP_T1 0x820D //33293 ()
#define PANEL_PWR_UP_T2 0x820E //33294 ()
#define PANEL_PWR_DN_T1 0x820F //33295 ()
#define PANEL_PWR_DN_T2 0x8210 //33296 ()
#define DP_SYNC_ADJUST_CTRL 0x8211 //33297 ()
#define ALT_DISP_HTOTAL_DELTA_0 0x8212 //33298 ()
#define ALT_DISP_HTOTAL_DELTA_1 0x8213 //33299 ()
#define ALT_DISP_HTOTAL_DELTA ALT_DISP_HTOTAL_DELTA_0
#define ALT_DISP_VTOTAL_0 0x8214 //33300 ()
#define ALT_DISP_VTOTAL_1 0x8215 //33301 ()
#define ALT_DISP_ADJ_LINES 0x8216 //33302 ()
#define DST_FREE_RUN_CNTRL 0x8218 //33304 ()
#define RED_CONTRAST_0 0x8220 //33312 ()
#define RED_CONTRAST_1 0x8221 //33313 ()
#define RED_CONTRAST RED_CONTRAST_0
#define GREEN_CONTRAST_0 0x8222 //33314 ()
#define GREEN_CONTRAST_1 0x8223 //33315 ()
#define GREEN_CONTRAST GREEN_CONTRAST_0
#define BLUE_CONTRAST_0 0x8224 //33316 ()
#define BLUE_CONTRAST_1 0x8225 //33317 ()
#define BLUE_CONTRAST BLUE_CONTRAST_0
#define RED_BRIGHTNESS 0x8226 //33318 ()
#define GREEN_BRIGHTNESS 0x8227 //33319 ()
#define BLUE_BRIGHTNESS 0x8228 //33320 ()
#define MULT_DITHER_CTRL 0x8229 //33321 ()
#define DISP_LUT_CTRL 0x8270 //33392 ()
#define POST_LUT_DITHER_CTRL 0x8271 //33393 ()
#define ADC_FILTER_CONFIG 0x8278
#define ADC_FILTER_DELTA_THRESH 0x8279
#define ADC_FILTER_LOW_THRESH 0x827A
#define ADC_FILTER_HIGH_THRESH 0x827B
#define FLICKER_OFFSET 0x8280 //33408 ()
#define NOFLICKER_OFFSET 0x8281 //33409 ()
#define FLICKER_FRAME_THRESH 0x8282 //33410 ()
#define NOFLICKER_FRAME_THRESH 0x8283 //33411 ()
#define FLICKER_SCORE_MIN_0 0x8284 //33412 ()
#define FLICKER_SCORE_MIN_1 0x8285 //33413 ()
#define FLICKER_SCORE_MIN_2 0x8286 //33414 ()
#define FLICKER_SCORE_MIN FLICKER_SCORE_MIN_0
#define FLICKER_SCORE_0 0x8288 //33416 ()
#define FLICKER_SCORE_1 0x8289 //33417 ()
#define FLICKER_SCORE_2 0x828A //33418 ()
#define VIRTUAL_EDID_CONTROL 0x8290 //33424 ()
#define VIRTUAL_EDID_DATA 0x8291 //33425 ()
#define VIRTUAL_EDID_ADDRESS 0x8292 //33426 ()
#define VIRTUAL_EDID_STATUS 0x8293 //33427 ()
#define MEM_TEST_SIGNATURE_CTRL 0x8294 //33428 ()
#define ROM_TEST_SIG_0 0x8296 //33430 ()
#define ROM_TEST_SIG_1 0x8297 //33431 ()
#define ROM_TEST_SIG_2 0x8298 //33432 ()
#define ADC_AUTST_LIN_DATA 0x82A9
#define ADC_AUTST_STATUS 0x82AA
#define ADC_AUTST_CTRL 0x82AB
#define ADC_AUTST_SEL 0x82AC
#define ADC_AUTST_HIT 0x82AD
#define CCF_TESTREG 0x82AE //33454 ()
#define RPLL_TEST_CONTROL 0x82AF
#define HDCP_CONTROL 0x82B0 //33456 ()
#define HDCP_ADDR 0x82B1 //33457 ()
#define HDCP_BKSV_0 0x82B2 //33458 ()
#define HDCP_BKSV_1 0x82B3 //33459 ()
#define HDCP_BKSV_2 0x82B4 //33460 ()
#define HDCP_BKSV_3 0x82B5 //33461 ()
#define HDCP_BKSV_4 0x82B6 //33462 ()
#define HDCP_STATUS 0x82B7 //33463 ()
#define DDC2B_CTRL1 0x82B8 //33464 ()
#define DDC2B_CTRL2 0x82B9 //33465 ()
#define DDC2B_STATUS 0x82BA //33466 ()
#define DDC2B_ADDR 0x82BB //33467 ()
#define DDC2B_CLOCK_STATUS 0x82BC //33468 ()
#define DDC2B_DATA 0x82BE //33470 ()
#define RSDS_LVDS_POWER 0x82C0 //33472 ()
#define RSDS_LVDS_DATA_CTRL 0x82C1 //33473 ()
#define LVDS_PLL_CTRL 0x82C2 //33474 ()
#define RSDS_LVDS_MISC1_CTRL 0x82C3 //33475 ()
#define RSDS_LVDS_MISC2_CTRL 0x82C4 //33476 ()
#define CLOCK_SIGNAL_DELAY 0x82C5 //33477 ()
#define RSDS_LVDS_TEST_CTRL 0x82C6 //33478 ()
#define LVDS_TEST_DATA 0x82C7 //33479 ()
#define LVDS_CLK_DATA 0x82C8 //33480 ()
// Reserved 0x82C9
#define TCON_CONTROL1 0x82D0 //33488 ()
#define TCON_CONTROL2 0x82D1 //33489 ()
#define TCON_PANEL_WIDTH_0 0x82D2 //33490 ()
#define TCON_PANEL_WIDTH_1 0x82D3 //33491 ()
#define TCON_SIGNAL_DELAY 0x82D4 //33492 ()
#define TCON_SIGNAL_POLARITY 0x82D6 //33494 ()
#define TCON_SIGNAL_ENABLE 0x82D7 //33495 ()
#define TCON_BLANKING_MASK 0x82D8 //33496 ()
#define ROE_ACTIVE_DELAY 0x82D9 //33497 ()
#define TCON_BLANKING_VSTART_0 0x82DA //33498 ()
#define TCON_BLANKING_VSTART_1 0x82DB //33499 ()
#define TCON_BLANKING_VEND_0 0x82DC //33500 ()
#define TCON_BLANKING_VEND_1 0x82DD //33501 ()
#define TCON_BLANKING_HOFFSET_0 0x82DE //33502 ()
#define TCON_BLANKING_HOFFSET_1 0x82DF //33503 ()
#define LP_HSTART_0 0x82E0 //33504 ()
#define LP_HSTART_1 0x82E1 //33505 ()
#define LP_HEND_0 0x82E2 //33506 ()
#define LP_HEND_1 0x82E3 //33507 ()
#define ESP_HSTART_0 0x82E4 //33508 ()
#define ESP_HSTART_1 0x82E5 //33509 ()
#define ESP_WIDTH 0x82E6 //33510 ()
#define OSP_HSTART_0 0x82E8 //33512 ()
#define OSP_HSTART_1 0x82E9 //33513 ()
#define OSP_WIDTH 0x82EA //33514 ()
#define POL_SWITCH_TIME_0 0x82EC //33516 ()
#define POL_SWITCH_TIME_1 0x82ED //33517 ()
#define ROWCLK_HSTART_0 0x82EE //33518 ()
#define ROWCLK_HSTART_1 0x82EF //33519 ()
#define ROWCLK_HEND_0 0x82F0 //33520 ()
#define ROWCLK_HEND_1 0x82F1 //33521 ()
#define RSP1_VSTART_0 0x82F2 //33522 ()
#define RSP1_VSTART_1 0x82F3 //33523 ()
#define RSP1_WIDTH 0x82F4 //33524 ()
#define POL_INVERSION_LENGTH 0x82F5 //33525 ()
#define ROE1_HSTART_0 0x82F6 //33526 ()
#define ROE1_HSTART_1 0x82F7 //33527 ()
#define ROE1_HEND_0 0x82F8 //33528 ()
#define ROE1_HEND_1 0x82F9 //33529 ()
#define ROE2_HSTART_0 0x82FA //33530 ()
#define ROE2_HSTART_1 0x82FB //33531 ()
#define ROE2_HEND_0 0x82FC //33532 ()
#define ROE2_HEND_1 0x82FD //33533 ()
#define BP0_CTRL 0x8300 //33536 ()
#define BP0_OCM_ADDR_0 0x8302 //33538 ()
#define BP0_OCM_ADDR_1 0x8303 //33539 ()
#define BP0_SUB_ADDR_0 0x8304 //33540 ()
#define BP0_SUB_ADDR_1 0x8305 //33541 ()
#define BP1_CTRL 0x8306 //33542 ()
#define BP1_OCM_ADDR_0 0x8308 //33544 ()
#define BP1_OCM_ADDR_1 0x8309 //33545 ()
#define BP1_SUB_ADDR_0 0x830A //33546 ()
#define BP1_SUB_ADDR_1 0x830B //33547 ()
#define BP2_CTRL 0x830C //33548 ()
#define BP2_OCM_ADDR_0 0x830E //33550 ()
#define BP2_OCM_ADDR_1 0x830F //33551 ()
#define BP2_SUB_ADDR_0 0x8310 //33552 ()
#define BP2_SUB_ADDR_1 0x8311 //33553 ()
#define BP3_CTRL 0x8312 //33554 ()
#define BP3_OCM_ADDR_0 0x8314 //33556 ()
#define BP3_OCM_ADDR_1 0x8315 //33557 ()
#define BP3_SUB_ADDR_0 0x8316 //33558 ()
#define BP3_SUB_ADDR_1 0x8317 //33559 ()
/****************************************************************************/
/* B I T D E F I N I T I O N S */
/****************************************************************************/
// HOST_CONTROL (0x8000)
#define SOFT_RESET BIT0
#define IPSYNC_UPDATE BIT1
#define DPSYNC_UPDATE BIT2
#define IPFORCE_UPDATE BIT3
#define DPFORCE_UPDATE BIT4
#define SYNC_UPDATE (IPSYNC_UPDATE | DPSYNC_UPDATE)
#define FORCE_UPDATE (IPFORCE_UPDATE | DPFORCE_UPDATE)
// CLOCK_CONFIG (0x8003)
#define IP_CLKSEL 0X03
#define IP_CLK_DVI 0x00
#define IP_CLK_EXT_DIV2 0x01
#define IP_CLK_RGB 0x02
#define IP_CLK_EXT_DIV 0x03
#define IFM_CLKSEL BIT2
#define IFM_CLK_TCLK 0x00
#define ACLK_SEL BIT3
#define ACLK_SDDS 0x00
#define OCM_CLKSEL 0X30
#define OCM_CLK_TCLK 0x00
#define OCM_CLK_F_DDS BIT4
#define OCM_CLK_GPIO3 BIT5
#define OCM_CLKSEL 0X30
#define DP_CLKSEL 0XC0
#define DP_CLK_IP_CLK_INV 0x00
#define DP_CLK_DCLK BIT6
#define DP_CLK_GPIO1 BIT7
#define DP_CLK_IPCLK 0xC0
// BYPASS (0x8006)
#define POWER_DOWN BIT0
#define CAPTURE_ONLY BIT1
#define TCON_LB_BYPASS BIT2
#define SCALER_PASSTHRU BIT3
#define P2S_BYPASS BIT4
#define TCON_SIGNALS_OFF BIT5
#define RSVR_BYPASS 0XC0
// IRQ_CONFIG (0x800B)
#define GPIO_IRQ_OUT_EN BIT0
#define IRQn_LATCHED BIT1
#define IRQn_ACTHIGH BIT2
// IFM_OCMMASK (0x800C)
#define OCM_NO_HS BIT0
#define OCM_NO_VS BIT1
#define OCM_HS_PERIOD_ERR BIT2
#define OCM_VS_PERIOD_ERR BIT3
#define OCM_DVI_DE_WIDTH_ERR BIT4
#define IP_ODD BIT6
#define OCM_INTLC_ERR BIT7
// INPUT_OCMMASK (0x800D)
#define OCM_IP_ACTIVE BIT0
#define OCM_IP_VBLANK BIT1
#define OCM_IP_LINEFLAG BIT2
#define IP_VS_FLAG BIT3
#define OCM_LBW_ADC_RDY BIT4
#define DDC2Bi_MASK BIT6
#define SPI_IRQ BIT7
// MISC_OCMMASK (0x800E)
#define OCM_D_ACTIVE BIT0
#define OCM_D_VBLANK BIT1
#define OCM_D_LINEFLAG BIT2
#define D_VS BIT3
#define OCM_AFR_ACTIVE BIT4
#define CLK_EVENT BIT6
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