register.h

GM5621原代码

	 #define FORCE_UPDATE								  (IPFORCE_UPDATE | DPFORCE_UPDATE)

    // CLOCK_CONFIG                               (0x3)
    #define IP_CLKSEL                             0X03
    #define IP_CLK_DVI                            0x00
    #define IP_CLK_VIDEO                          0x01
    #define IP_CLK_RGB                            0x02
    #define IFM_CLKSEL                            BIT2
    #define IFM_CLK_TCLK                          0x00
    #define IFM_CLK_GPIO4                         BIT2
    #define ACLK_SEL                              BIT3
    #define ACLK_SDDS                             0x00
    #define ACLK_ADC_DEL_ACLK                     BIT3
    #define OCM_CLKSEL                            0X30
    #define OCM_CLK_TCLK                          0x00
    #define OCM_CLK_F_DDS                         BIT4
    #define OCM_CLK_GPIO3                         BIT5
    #define DP_CLKSEL                             0XC0
    #define DP_CLK_IP_CLK_INV                     0x00
    #define DP_CLK_DCLK                           BIT6
    #define DP_CLK_GPIO1                          BIT7
    #define DP_CLK_IPCLK                          0xC0

  
    // LATCHED_BOOT                               (0x5)
    // user bits [5:0] correspond to address lines A[12:7] on the 5221AA
    #define USER_BITS                             0X3F
    #define FORCEXROM						      BIT0
	#define SKIPXROMBOOT						  BIT1
	#define LATCHED_BOOT_CONFIG						3 // for seleted ignore crc, signature option
	#define DOCRCCHECK							  3  // BOTH FORCEXROM and SKIPXROMBOOT set means check crc and signature
    #define TCLKSEL							      0x18
    #define TCLKSEL_START					      3
    #define DDCHANSEL						      BIT5
    #define DDCHANSEL_START					      5
    #define OCM_USES_TCLK                         BIT2
	 #define OCM_CLK_FCLK                          0x10


    // BYPASS                                     (0x6)
    #define POWER_DOWN                            BIT0
    #define CAPTURE_ONLY                          BIT1
    #define SCALER_PASSTHRU                       BIT3

    // TIMING_CONFIG                              (0x7)
    #define DP_TIMING                             0X07

    // PADDRIVE1                                  (0x8)
    #define DP_DCLKDRIVE                          0X0F
    #define DP_VSDRIVE                            0XF0

    // PADDRIVE2                                  (0x9)
    #define PD_DATADRIVE_E                        0X0F
    #define PD_DATADRIVE_O                        0XF0

    // PADDRIVE3                                  (0xA)
    #define DP_HSDRIVE                            0X0F
    #define DP_DEDRIVE                            0XF0

    // IRQ_CONFIG                                 (0xB)
    #define GPIO_IRQ_OUT_EN                       BIT0
    #define IRQn_LATCHED                          BIT1
    #define IRQn_ACTHIGH                          BIT2
    #define GPIO_IRQ_IN_EN                        BIT4

    // IFM_OCMMASK                                (0xC)
	 #define OCM_NO_HS                             BIT0
	 #define OCM_NO_VS                             BIT1
	 #define OCM_HS_PERIOD_ERR                     BIT2
	 #define OCM_VS_PERIOD_ERR                     BIT3
	 #define OCM_DVI_DE_WIDTH_ERR                  BIT4
    #define IP_ODD                                BIT6
	 #define OCM_INTLC_ERR                         BIT7

    // INPUT_OCMMASK                              (0xD)
	 #define OCM_IP_ACTIVE                             BIT0
	 #define OCM_IP_VBLANK                             BIT1
	 #define OCM_IP_LINEFLAG                           BIT2
	 #define IP_VS_FLAG                            BIT3
	 #define OCM_LBW_ADC_RDY                           BIT4
	 #define I2C_MASTER                            BIT5
	 #define DDC2Bi_MASK                                BIT6
	 #define SPI_IRQ                               BIT7

	 // MISC_OCMMASK                               (0xE)
	 #define OCM_D_ACTIVE                              BIT0
	 #define OCM_D_VBLANK                              BIT1
	 #define OCM_D_LINEFLAG                            BIT2
    #define D_VS                                  BIT3
    #define OM_AFR_ACTIVE                         BIT4
    #define CLK_EVENT                             BIT6
    #define BP_IRQ                                BIT7

    // SYSTEM_STATUS                              (0xF)
//    #define IP_ODD                                BIT2
    #define IFM_IRQ                               BIT3
    #define INPUT_IRQ                             BIT4
    #define DISPLAY_IRQ                           BIT5
    #define CLOCK_IRQ                             BIT6

    // IFM_STATUS                                 (0x10)
    #define NO_HS                                 BIT0
	 #define NO_VS                                 BIT1
    #define HS_PERIOD_ERR                         BIT2
	 #define VS_PERIOD_ERR                         BIT3
	 #define DVI_DE_WIDTH_ERR                      BIT4
//    #define BP_IRQ                                BIT5
	 #define INTLC_ERR                             BIT7

    // INPUT_STATUS                               (0x11)
	 #define IP_ACTIVE                             BIT0
    #define IP_VBLANK                             BIT1
    #define IP_LINEFLAG                           BIT2
    #define INPUT_VS                              BIT3
    #define LBW_ADC_RDY                           BIT4
    #define I2C_MASTER_RDY                        BIT5
    #define DDC2BI_IRQ                            BIT6
    #define SPI_EXCH_FLAG                         BIT7

    // DISPLAY_STATUS                             (0x12)
	 #define D_ACTIVE                              BIT0
	 #define D_VBLANK                              BIT1
    #define D_LINEFLAG                            BIT2
    #define D_VS_FLAG                             BIT3
    #define D_VS_LEVEL                            BIT4
    #define D_VACTIVE                             BIT5
    #define AFR_ACTIVE                            BIT6
    #define BUFFER_OVERRUN                        BIT7

    // CLOCK_STATUS                               (0x13)
    #define SRC_NOCLK                             BIT0
    #define SRC_CLKERR                            BIT1
    #define SDDS_OPENLOOP                         BIT2
    #define DDDS_OPENLOOP                         BIT3
    #define CLKMEAS_OFLOW                         BIT4

    // MISC_STATUS                                (0x14)
    #define IP_VS                                 BIT0
    #define IP_VACTIVE                            BIT1
    #define ADC_CAL                               BIT2

    // RCLK_CONFIG                                (0x16)
    #define RCLK_POWER_DN                         BIT3
    #define RCLK_RESET                            BIT4

    // RCLK_FREQUENCY                             (0x17)
    #define RCLK_N                                0X1F
    #define RCLK_M                                0X60

    // RCLK_PLL                                   (0x18)
    #define RCLK_BW_4M                            BIT0
    #define RCLK_BW_H                             BIT1
    #define RCLK_BW_TRACK                         BIT2
    #define AGCON                                 BIT5
    #define OSCI                                  BIT6

  
    // OCM_BUS_CONTROL_0                          (0x20)
    #define ENABLE_WDT                            BIT0
    #define EN_WDT_INTERRUPT                      BIT1
    #define OCM_RAM_CTRL                          0X0C

   // OCM_BUS_WDT_STATUS 						  (0x23)
   	#define TRANSACTION_ERR							1
    // OCM_CONTROL                                (0x27)
    #define OCM_RESET                             BIT0
    #define INT_ROM_EN                            BIT4

    // EXT_ROM_WR_CTRL                            (0x28)
    #define XROM_WE_WIDTH                         0X1F
    #define XROM_WE_AS                            0X60

    // EXT_ROM_RD_CTRL                            (0x29)
    #define XROM_OE_WIDTH                         0X1F

    // SPI_CONTROL                                (0x2A)
    #define SPI_CPHA                              BIT0
    #define SPI_CLK_INV                           BIT1
    #define SPI_BYTE_EX                           BIT2
    #define SPI_PROGRAM_EN                        BIT3
    #define SPI_CLK_SEL                           0X70
    #define FLASH_CHIP_SEL                        BIT7

    // SPI_STATUS                                 (0x2B)
    #define SPI_EXCH_ACTIVE                       BIT0
    #define SPI_WRITE_ERROR                       BIT1
    #define SPI_DMA_BUSY                          BIT2

 
    // SPI_CACHE_CTRL                             (0x2E)
    #define SPI_CACHE_EN                          BIT0
    #define CACHE_FILL_LINE                       BIT1
    #define CACHE_DMA_EN                          BIT2
    #define SPI_CACHE_CLR                         BIT3

    // PWM0_CONFIG                                (0x30)
    #define PWM0_GPIOn_EN                         BIT0
    #define PWM0_CLKSEL                           BIT1
    #define PWM0_PRESCALE                         0X0C
    #define PWM0_VSRESET                          BIT4
    #define PWM0_10BIT