📄 register.h
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#define ACM_INTP_TAG7 0x823C //572 (CC_LO)
#define ACM_INTP_TAG8 0x823D //573 (CC_HI)
#define MULT_CTRL 0x823E //574 (CC_LO)
#define MULT_DITHER_CTRL 0x823F //575 (CC_HI)
#define MULT_COEFF_11_A_0 0x8240 //576 (CC_LO)
#define MULT_COEFF_11_A_1 0x8241 //577 (CC_HI)
#define MULT_COEFF_12_A_0 0x8242 //578 (CC_LO)
#define MULT_COEFF_12_A_1 0x8243 //579 (CC_HI)
#define MULT_COEFF_13_A_0 0x8244 //580 (CC_LO)
#define MULT_COEFF_13_A_1 0x8245 //581 (CC_HI)
#define MULT_COEFF_21_A_0 0x8246 //582 (CC_LO)
#define MULT_COEFF_21_A_1 0x8247 //583 (CC_HI)
#define MULT_COEFF_22_A_0 0x8248 //584 (CC_LO)
#define MULT_COEFF_22_A_1 0x8249 //585 (CC_HI)
#define MULT_COEFF_23_A_0 0x824A //586 (CC_LO)
#define MULT_COEFF_23_A_1 0x824B //587 (CC_HI)
#define MULT_COEFF_31_A_0 0x824C //588 (CC_LO)
#define MULT_COEFF_31_A_1 0x824D //589 (CC_HI)
#define MULT_COEFF_32_A_0 0x824E //590 (CC_LO)
#define MULT_COEFF_32_A_1 0x824F //591 (CC_HI)
#define MULT_COEFF_33_A_0 0x8250 //592 (CC_LO)
#define MULT_COEFF_33_A_1 0x8251 //593 (CC_HI)
#define MULT_OFFSET1_A 0x8252 //594 (CC_LO)
#define MULT_OFFSET2_A 0x8253 //595 (CC_HI)
#define MULT_OFFSET3_A 0x8254 //596 (CC_LO)
#define MULT_COEFF_11_B_0 0x8256 //598 (CC_LO)
#define MULT_COEFF_11_B_1 0x8257 //599 (CC_HI)
#define MULT_COEFF_12_B_0 0x8258 //600 (CC_LO)
#define MULT_COEFF_12_B_1 0x8259 //601 (CC_HI)
#define MULT_COEFF_13_B_0 0x825A //602 (CC_LO)
#define MULT_COEFF_13_B_1 0x825B //603 (CC_HI)
#define MULT_COEFF_21_B_0 0x825C //604 (CC_LO)
#define MULT_COEFF_21_B_1 0x825D //605 (CC_HI)
#define MULT_COEFF_22_B_0 0x825E //606 (CC_LO)
#define MULT_COEFF_22_B_1 0x825F //607 (CC_HI)
#define MULT_COEFF_23_B_0 0x8260 //608 (CC_LO)
#define MULT_COEFF_23_B_1 0x8261 //609 (CC_HI)
#define MULT_COEFF_31_B_0 0x8262 //610 (CC_LO)
#define MULT_COEFF_31_B_1 0x8263 //611 (CC_HI)
#define MULT_COEFF_32_B_0 0x8264 //612 (CC_LO)
#define MULT_COEFF_32_B_1 0x8265 //613 (CC_HI)
#define MULT_COEFF_33_B_0 0x8266 //614 (CC_LO)
#define MULT_COEFF_33_B_1 0x8267 //615 (CC_HI)
#define MULT_OFFSET1_B 0x8268 //616 (CC_LO)
#define MULT_OFFSET2_B 0x8269 //617 (CC_HI)
#define MULT_OFFSET3_B 0x826A //618 (CC_LO)
#define DISP_LUT_CTRL 0x8270 //624 (DP_LO)
#define POST_LUT_DITHER_CTRL 0x8271 //625 (DP_HI)
#define ADC_FILTER_CONFIG 0x8290 //656 (ADC_LO)
#define ADC_FILTER_DELTA_THRESH 0x8291 //657 (ADC_HI)
#define ADC_FILTER_LOW_THRESH 0x8292 //658 (ADC_LO)
#define ADC_FILTER_HIGH_THRESH 0x8293 //659 (ADC_HI)
#define TEST_CTRL_0 0x82A0 //672 (HOST_LO)
#define TEST_CTRL_1 0x82A1 //673 (HOST_HI)
#define TESTBUS_A_SEL 0x82A2 //674 (HOST_LO)
#define TESTBUS_B_SEL 0x82A3 //675 (HOST_HI)
#define TEST_INFO 0x82A4 //676 (HOST_LO)
#define TEST_MEM_CTRL 0x82A5 //677 (HOST_HI)
#define TEST_SIG_0 0x82A6 //678 (HOST_LO)
#define TEST_SIG_1 0x82A7 //679 (HOST_HI)
#define TEST_SIG_2 0x82A8 //680 (HOST_LO)
#define ADC_AUTST_LIN_DATA 0x82A9 //681 (HOST_HI)
#define ADC_AUTST_STATUS 0x82AA //682 (HOST_LO)
#define ADC_AUTST_CTRL 0x82AB //683 (ADC_HI)
#define ADC_AUTST_SEL 0x82AC //684 (ADC_LO)
#define ADC_AUTST_HIT 0x82AD //685 (ADC_HI)
#define CCF_TESTREG 0x82AE //686 (HOST_LO)
#define RPLL_TEST_CONTROL 0x82AF //687 (HOST_HI)
#define HDCP_CONTROL 0x82B0 //688 (IP_LO)
#define HDCP_ADDR 0x82B1 //689 (IP_HI)
#define HDCP_BKSV0 0x82B2 //690 (IP_LO)
#define HDCP_BKSV1 0x82B3 //691 (IP_HI)
#define HDCP_BKSV2 0x82B4 //692 (IP_LO)
#define HDCP_BKSV3 0x82B5 //693 (IP_HI)
#define HDCP_BKSV4 0x82B6 //694 (IP_LO)
#define HDCP_STATUS 0x82B7 //695 (IP_HI)
#define DDC2B_CTRL_0 0x82B8 //696 (OCM_LO)
#define DDC2B_CTRL_1 0x82B9 //697 (OCM_HI)
#define DDC2B_STATUS 0x82BA //698 (OCM_LO)
#define DDC2B_ADDR 0x82BB //699 (OCM_HI)
#define DDC2B_DATA 0x82BC //700 (OCM_LO)
#define LVDS_POWER 0x82C0 //704 (DP_LO)
#define LVDS_DIGITAL_CTRL 0x82C1 //705 (DP_HI)
#define LVDS_PLL_CTRL 0x82C2 //706 (DP_LO)
#define LVDS_MISC_CTRL 0x82C3 //707 (DP_HI)
#define LVDS_P2S_CTRL0 0x82C4 //708 (DP_LO)
#define LVDS_P2S_CTRL1 0x82C5 //709 (DP_HI)
#define LVDS_TEST_CTRL 0x82C6 //710 (DP_LO)
#define LVDS_TEST_DATA 0x82C7 //711 (DP_HI)
#define LVDS_CLK_DATA 0x82C8 //712 (DP_LO)
#define LVDS_MISC2 0x82C9 //713 (DP_HI)
#define BP0_CTRL 0x8300 //768 (CORE_LO)
#define BP0_ADDR_EXTRA 0x8301 //769 (CORE_HI)
#define BP0_OCM_ADDR_0 0x8302 //770 (CORE_LO)
#define BP0_OCM_ADDR_1 0x8303 //771 (CORE_HI)
#define BP0_SUB_ADDR_0 0x8304 //772 (CORE_LO)
#define BP0_SUB_ADDR_1 0x8305 //773 (CORE_HI)
#define BP1_CTRL 0x8306 //774 (CORE_LO)
#define BP1_ADDR_EXTRA 0x8307 //775 (CORE_HI)
#define BP1_OCM_ADDR_0 0x8308 //776 (CORE_LO)
#define BP1_OCM_ADDR_1 0x8309 //777 (CORE_HI)
#define BP1_SUB_ADDR_0 0x830A //778 (CORE_LO)
#define BP1_SUB_ADDR_1 0x830B //779 (CORE_HI)
#define BP2_CTRL 0x830C //780 (CORE_LO)
#define BP2_ADDR_EXTRA 0x830D //781 (CORE_HI)
#define BP2_OCM_ADDR_0 0x830E //782 (CORE_LO)
#define BP2_OCM_ADDR_1 0x830F //783 (CORE_HI)
#define BP2_SUB_ADDR_0 0x8310 //784 (CORE_LO)
#define BP2_SUB_ADDR_1 0x8311 //785 (CORE_HI)
#define BP3_CTRL 0x8312 //786 (CORE_LO)
#define BP3_ADDR_EXTRA 0x8313 //787 (CORE_HI)
#define BP3_OCM_ADDR_0 0x8314 //788 (CORE_LO)
#define BP3_OCM_ADDR_1 0x8315 //789 (CORE_HI)
#define BP3_SUB_ADDR_0 0x8316 //790 (CORE_LO)
#define BP3_SUB_ADDR_1 0x8317 //791 (CORE_HI)
#define BP4_CTRL 0x8318 //792 (CORE_LO)
#define BP4_ADDR_EXTRA 0x8319 //793 (CORE_HI)
#define BP4_OCM_ADDR_0 0x831A //794 (CORE_LO)
#define BP4_OCM_ADDR_1 0x831B //795 (CORE_HI)
#define BP4_SUB_ADDR_0 0x831C //796 (CORE_LO)
#define BP4_SUB_ADDR_1 0x831D //797 (CORE_HI)
#define BP5_CTRL 0x831E //798 (CORE_LO)
#define BP5_ADDR_EXTRA 0x831F //799 (CORE_HI)
#define BP5_OCM_ADDR_0 0x8320 //800 (CORE_LO)
#define BP5_OCM_ADDR_1 0x8321 //801 (CORE_HI)
#define BP5_SUB_ADDR_0 0x8322 //802 (CORE_LO)
#define BP5_SUB_ADDR_1 0x8323 //803 (CORE_HI)
#define BP6_CTRL 0x8324 //804 (CORE_LO)
#define BP6_ADDR_EXTRA 0x8325 //805 (CORE_HI)
#define BP6_OCM_ADDR_0 0x8326 //806 (CORE_LO)
#define BP6_OCM_ADDR_1 0x8327 //807 (CORE_HI)
#define BP6_SUB_ADDR_0 0x8328 //808 (CORE_LO)
#define BP6_SUB_ADDR_1 0x8329 //809 (CORE_HI)
#define BP7_CTRL 0x832A //810 (CORE_LO)
#define BP7_ADDR_EXTRA 0x832B //811 (CORE_HI)
#define BP7_OCM_ADDR_0 0x832C //812 (CORE_LO)
#define BP7_OCM_ADDR_1 0x832D //813 (CORE_HI)
#define BP7_SUB_ADDR_0 0x832E //814 (CORE_LO)
#define BP7_SUB_ADDR_1 0x832F //815 (CORE_HI)
#define BP8_CTRL 0x8330 //816 (CORE_LO)
#define BP8_ADDR_EXTRA 0x8331 //817 (CORE_HI)
#define BP8_OCM_ADDR_0 0x8332 //818 (CORE_LO)
#define BP8_OCM_ADDR_1 0x8333 //819 (CORE_HI)
#define BP8_SUB_ADDR_0 0x8334 //820 (CORE_LO)
#define BP8_SUB_ADDR_1 0x8335 //821 (CORE_HI)
#define BP9_CTRL 0x8336 //822 (CORE_LO)
#define BP9_ADDR_EXTRA 0x8337 //823 (CORE_HI)
#define BP9_OCM_ADDR_0 0x8338 //824 (CORE_LO)
#define BP9_OCM_ADDR_1 0x8339 //825 (CORE_HI)
#define BP9_SUB_ADDR_0 0x833A //826 (CORE_LO)
#define BP9_SUB_ADDR_1 0x833B //827 (CORE_HI)
#define BP10_CTRL 0x833C //828 (CORE_LO)
#define BP10_ADDR_EXTRA 0x833D //829 (CORE_HI)
#define BP10_OCM_ADDR_0 0x833E //830 (CORE_LO)
#define BP10_OCM_ADDR_1 0x833F //831 (CORE_HI)
#define BP10_SUB_ADDR_0 0x8340 //832 (CORE_LO)
#define BP10_SUB_ADDR_1 0x8341 //833 (CORE_HI)
#define BP11_CTRL 0x8342 //834 (CORE_LO)
#define BP11_ADDR_EXTRA 0x8343 //835 (CORE_HI)
#define BP11_OCM_ADDR_0 0x8344 //836 (CORE_LO)
#define BP11_OCM_ADDR_1 0x8345 //837 (CORE_HI)
#define BP11_SUB_ADDR_0 0x8346 //838 (CORE_LO)
#define BP11_SUB_ADDR_1 0x8347 //839 (CORE_HI)
#define BP12_CTRL 0x8348 //840 (CORE_LO)
#define BP12_ADDR_EXTRA 0x8349 //841 (CORE_HI)
#define BP12_OCM_ADDR_0 0x834A //842 (CORE_LO)
#define BP12_OCM_ADDR_1 0x834B //843 (CORE_HI)
#define BP12_SUB_ADDR_0 0x834C //844 (CORE_LO)
#define BP12_SUB_ADDR_1 0x834D //845 (CORE_HI)
#define BP13_CTRL 0x834E //846 (CORE_LO)
#define BP13_ADDR_EXTRA 0x834F //847 (CORE_HI)
#define BP13_OCM_ADDR_0 0x8350 //848 (CORE_LO)
#define BP13_OCM_ADDR_1 0x8351 //849 (CORE_HI)
#define BP13_SUB_ADDR_0 0x8352 //850 (CORE_LO)
#define BP13_SUB_ADDR_1 0x8353 //851 (CORE_HI)
#define BP14_CTRL 0x8354 //852 (CORE_LO)
#define BP14_ADDR_EXTRA 0x8355 //853 (CORE_HI)
#define BP14_OCM_ADDR_0 0x8356 //854 (CORE_LO)
#define BP14_OCM_ADDR_1 0x8357 //855 (CORE_HI)
#define BP14_SUB_ADDR_0 0x8358 //856 (CORE_LO)
#define BP14_SUB_ADDR_1 0x8359 //857 (CORE_HI)
#define BP15_CTRL 0x835A //858 (CORE_LO)
#define BP15_ADDR_EXTRA 0x835B //859 (CORE_HI)
#define BP15_OCM_ADDR_0 0x835C //860 (CORE_LO)
#define BP15_OCM_ADDR_1 0x835D //861 (CORE_HI)
#define BP15_SUB_ADDR_0 0x835E //862 (CORE_LO)
#define BP15_SUB_ADDR_1 0x835F //863 (CORE_HI)
/****************************************************************************/
/* B I T D E F I N I T I O N S */
/****************************************************************************/
// HOST_CONTROL (0x0)
#define SOFT_RESET BIT0
#define IPSYNC_UPDATE BIT1
#define DPSYNC_UPDATE BIT2
#define IPFORCE_UPDATE BIT3
#define DPFORCE_UPDATE BIT4
#define SYNC_UPDATE (IPSYNC_UPDATE | DPSYNC_UPDATE)
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