📄 register.h
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/*
$Workfile: Register.h $
$Revision: 1.47 $
$Date: Jan 03 2005 22:38:40 $
*/
/****************************************************************************/
/* */
/* Copyright (C) 2003. GENESIS MICROCHIP INC. */
/* All rights reserved. No part of this program may be reproduced. */
/* */
/* Genesis Microchip Inc., 165 Commerce Valley Dr. West */
/* Thornhill, Ontario, Canada, L3T 7V8 */
/* */
/*==========================================================================*/
#ifndef __REGS_H__
#define __REGS_H__
/**************************************************************************/
/* I N T E R N A L O C M R A M M E M O R Y M A P */
/**************************************************************************/
#define IRAM_OSDSRAMStart 0x00000
#define IRAM_OSDSRAMSize 0x07FFF
#define IRAM_OSDColorLUTStart 0x08400
#define IRAM_OSDColorLUTSize 0x003FF
#define IRAM_ColorControlStart 0x08800
#define IRAM_ColorControlSize 0x007FF
#define IRAM_DisplayGammaLUTStart 0x09000
#define IRAM_DisplayGammaLUTSize 0x00FFF
#define IRAM_HDCPKeyRAMStart 0x0A400
#define IRAM_HDCPKeyRAMSize 0x003FF
#define IRAM_DisplayLineBufferStart 0x10000
#define IRAM_DisplayLineBufferSize 0x07FFF
/**************************************************************************/
/* C H I P S P E C I F I C C O N S T A N T S */
/**************************************************************************/
// (PanelMinHTotal - PanelWidth) > 53
// Display horizontal timing has a blanking time of 54 DCLKs minimum
#define DISPLAY_HORIZONTAL_BLANKING_MIN (54 - 1)
// Highlight window must have a minimum Horizontal Front Porch of 27 DCLKs
#define HIGHLIGHT_WINDOW_FRONT_PORCH (27 - 1)
#define DV_TOTAL_MAX_VALUE 0x07FF // reg. DV_TOTAL is 11 bits wide.
/**************************************************************************/
/* R E G I S T E R D E F I N I T I O N S */
/**************************************************************************/
#define HOST_CONTROL 0x8000 //0 (HOST_LO)
#define PRODUCT_ID 0x8001 //1 (HOST_HI)
#define PRODUCT_REV 0x8002 //2 (HOST_LO)
#define CLOCK_CONFIG 0x8003 //3 (HOST_HI)
#define OCM_TCLK_DIV 0x8004 //4 (HOST_LO)
#define LATCHED_BOOT 0x8005 //5 (HOST_HI)
#define BYPASS 0x8006 //6 (HOST_LO)
#define TIMING_CONFIG 0x8007 //7 (HOST_HI)
#define PADDRIVE1 0x8008 //8 (HOST_LO)
#define PADDRIVE2 0x8009 //9 (HOST_HI)
#define PADDRIVE3 0x800A //10 (HOST_LO)
#define PADDRIVE PADDRIVE1
#define IRQ_CONFIG 0x800B //11 (HOST_HI)
#define IFM_OCMMASK 0x800C //12 (HOST_LO)
#define INPUT_OCMMASK 0x800D //13 (HOST_HI)
#define MISC_OCMMASK 0x800E //14 (HOST_LO)
#define SYSTEM_STATUS 0x800F //15 (HOST_HI)
#define IFM_STATUS 0x8010 //16 (HOST_LO)
#define INPUT_STATUS 0x8011 //17 (HOST_HI)
#define DISPLAY_STATUS 0x8012 //18 (HOST_LO)
#define CLOCK_STATUS 0x8013 //19 (HOST_HI)
#define MISC_STATUS 0x8014 //20 (HOST_LO)
#define RCLK_CONFIG 0x8016 //22 (DDS_LO)
#define RCLK_FREQUENCY 0x8017 //23 (DDS_HI)
#define RCLK_PLL 0x8018 //24 (DDS_LO)
#define FCLK_FREQ_0 0x801A //26 (DDS_LO)
#define FCLK_FREQ_1 0x801B //27 (DDS_HI)
#define FCLK_FREQ FCLK_FREQ_0
#define LCLK_FREQ_0 0x801C //28 (DDS_LO)
#define LCLK_FREQ_1 0x801D //29 (DDS_HI)
#define LCLK_FREQ LCLK_FREQ_0
#define OCM_BUS_CONTROL_0 0x8020 //32 (CORE_LO)
#define OCM_WBUF_STATUS 0x8021 //33 (CORE_HI)
#define OCM_BUS_WDT_INIT_1 0x8022 //34 (CORE_LO)
#define OCM_BUS_WDT_STATUS 0x8023 //35 (CORE_HI)
#define OCM_WDT_ERR_ADDR_0 0x8024 //36 (CORE_LO)
#define OCM_WDT_ERR_ADDR_1 0x8025 //37 (CORE_HI)
#define OCM_WDT_ERR_ADDR_2 0x8026 //38 (CORE_LO)
#define OCM_CONTROL 0x8027 //39 (HOST_HI)
#define EXT_ROM_WR_CTRL 0x8028 //40 (CORE_LO)
#define EXT_ROM_RD_CTRL 0x8029 //41 (CORE_HI)
#define SPI_CONTROL 0x802A //42 (CORE_LO)
#define SPI_STATUS 0x802B //43 (CORE_HI)
#define SPI_DATA_0 0x802C //44 (CORE_LO)
#define SPI_DATA_1 0x802D //45 (CORE_HI)
#define SPI_CACHE_CTRL 0x802E //46 (CORE_LO)
#define PWM0_CONFIG 0x8030 //48 (HOST_LO)
#define PWM0_PERIOD 0x8031 //49 (HOST_HI)
#define PWM0_PULSE 0x8032 //50 (HOST_LO)
#define PWM1_CONFIG 0x8033 //51 (HOST_HI)
#define PWM1_PERIOD 0x8034 //52 (HOST_LO)
#define PWM1_PULSE 0x8035 //53 (HOST_HI)
#define PWM2_CONFIG 0x8036 //54 (HOST_LO)
#define PWM2_PERIOD 0x8037 //55 (HOST_HI)
#define PWM2_PULSE 0x8038 //56 (HOST_LO)
#define PWM3_CONFIG 0x8039 //57 (HOST_HI)
#define PWM3_PERIOD 0x803A //58 (HOST_LO)
#define PWM3_PULSE 0x803B //59 (HOST_HI)
#define GPIO_DIRCTRL1 0x803C //60 (HOST_LO)
#define GPO_OPENDRAIN_EN1 0x803D //61 (HOST_HI)
#define GPINPUT1 0x803E //62 (HOST_LO)
#define GPOUTPUT1 0x803F //63 (HOST_HI)
#define GPIO_DIRCTRL2 0x8040 //64 (HOST_LO)
#define GPO_OPENDRAIN_EN2 0x8041 //65 (HOST_HI)
#define GPINPUT2 0x8042 //66 (HOST_LO)
#define GPOUTPUT2 0x8043 //67 (HOST_HI)
#define GPIO_DIRCTRL3 0x8044 //68 (HOST_LO)
#define GPO_OPENDRAIN_EN3 0x8045 //69 (HOST_HI)
#define GPINPUT3 0x8046 //70 (HOST_LO)
#define GPOUTPUT3 0x8047 //71 (HOST_HI)
#define LOW_BW_ADC_CTRL 0x8048 //72 (HOST_LO)
#define LOW_BW_ADC_RESULT 0x8049 //73 (HOST_HI)
#define LOW_BW_ADC_STATUS 0x804A //74 (HOST_LO)
#define LOW_BW_ADC_TEST 0x804B //75 (HOST_HI)
#define I2C_MST_CTRL 0x8050 //80 (OCM_LO)
#define I2C_MST_DMA_CNTR 0x8051 //81 (OCM_HI)
#define I2C_MST_CLK_SCALE_0 0x8052 //82 (OCM_LO)
#define I2C_MST_CLK_SCALE_1 0x8053 //83 (OCM_HI)
#define I2C_MST_TX_CTRL 0x8054 //84 (OCM_LO)
#define I2C_MST_TX_DATA 0x8055 //85 (OCM_HI)
#define I2C_MST_STATUS 0x8056 //86 (OCM_LO)
#define I2C_MST_RX_DATA 0x8057 //87 (OCM_HI)
#define VPORT_CTRL 0x8058 //88 (IP_LO)
#define ADC_CONTROL 0x8060 //96 (ADC_LO)
#define ADC_CLAMPSTART 0x8061 //97 (ADC_HI)
#define ADC_CLAMPWIDTH 0x8062 //98 (ADC_LO)
#if !defined(GSEL_BUILD) && !defined(APP_BUILD)
#define ADC_FAS0 0x8064 //100 (ADC_LO)
#define ADC_FAS1 0x8065 //101 (ADC_HI)
#else /* latest universal register names used in GSEL */
#define ADC_FAS1 0x8064 //100 (ADC_LO)
#define ADC_FAS2 0x8065 //101 (ADC_HI)
#endif
#define ADC_TEST1 0x8066 //102 (ADC_LO)
#define ADC_TEST2 0x8067 //103 (ADC_HI)
#define ADC_DATA_RED 0x8068 //104 (ADC_LO)
#define ADC_DATA_GRN 0x8069 //105 (ADC_HI)
#define ADC_DATA_BLU 0x806A //106 (ADC_LO)
#define ADC_FLAGS 0x806B //107 (HOST_HI)
#define RED_OFFSET1 0x806C //108 (ADC_LO)
#define RED_OFFSET2 0x806D //109 (ADC_HI)
#define RED_GAIN RED_GAIN_0
#define RED_GAIN_0 0x806E //110 (ADC_LO)
#define RED_GAIN_1 0x806F //111 (ADC_HI)
#define GRN_OFFSET1 0x8070 //112 (ADC_LO)
#define GRN_OFFSET2 0x8071 //113 (ADC_HI)
#define GRN_GAIN GRN_GAIN_0
#define GRN_GAIN_0 0x8072 //114 (ADC_LO)
#define GRN_GAIN_1 0x8073 //115 (ADC_HI)
#define BLU_OFFSET1 0x8074 //116 (ADC_LO)
#define BLU_OFFSET2 0x8075 //117 (ADC_HI)
#define BLU_GAIN BLU_GAIN_0
#define BLU_GAIN_0 0x8076 //118 (ADC_LO)
#define BLU_GAIN_1 0x8077 //119 (ADC_HI)
#define ADC_TESTDAC 0x8078 //120 (ADC_LO)
#define ADC_DAC_DATA 0x8079 //121 (ADC_HI)
#define ADC_MODULATION 0x807A //122 (ADC_LO)
#define MISSING_CODE_TEST 0x807B //123 (ADC_HI)
#define ADC_RGB_PHASE 0x807C //124 (ADC_LO)
#define SYNC_TIP_CLAMP_END 0x807D //125 (ADC_HI)
#define SYNC_TIP_CLAMP_TIME_OUT 0x807E //126 (ADC_LO)
#define DVI_CTRL 0x8080 //128 (IP_LO)
#define DVI_EQUALIZATION 0x8081 //129 (IP_HI)
#define DVI_CONFIG 0x8082 //130 (IP_LO)
#define DVI_DE 0x8083 //131 (IP_HI)
#define DVI_PLL 0x8084 //132 (IP_LO)
#define DVI_PHASEPICK3 0x8085 //133 (IP_HI)
#define DVI_PHASEPICK2 0x8086 //134 (IP_LO)
#define DVI_PHASEPICK1 0x8087 //135 (IP_HI)
#define DVI_MISC 0x8088 //136 (IP_LO)
#define DVI_TESTCTRL 0x8089 //137 (IP_HI)
#define DVI_TEST 0x808A //138 (IP_LO)
#define DVI_PHASE_ADJ 0x808B //139 (IP_HI)
#define DVI_SIGQUAL_0 0x808C //140 (IP_LO)
#define DVI_SIGQUAL_1 0x808D //141 (IP_HI)
#define DVI_SIGQUAL_2 0x808E //142 (IP_LO)
#define DVI_SIGQUAL DVI_SIGQUAL_0
#define DVI_PHASE_A_SCORE_0 0x8090 //144 (IP_LO)
#define DVI_PHASE_A_SCORE_1 0x8091 //145 (IP_HI)
#define DVI_PHASE_A_SCORE_2 0x8092 //146 (IP_LO)
#define DVI_PHASE_B_SCORE_0 0x8094 //148 (IP_LO)
#define DVI_PHASE_B_SCORE1 0x8095 //149 (IP_HI)
#define DVI_PHASE_B_SCORE_2 0x8096 //150 (IP_LO)
#define DVI_PHASE_C_SCORE_0 0x8098 //152 (IP_LO)
#define DVI_PHASE_C_SCORE_1 0x8099 //153 (IP_HI)
#define DVI_PHASE_C_SCORE_2 0x809A //154 (IP_LO)
#define DVI_RCAL_RESULT_0 0x809C //156 (IP_LO)
#define DVI_RCAL_RESULT_1 0x809E //158 (IP_LO)
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