📄 register_57xx.h
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#define MULT_COEFF_12_B_1 0x825B //601 (CC_HI)
#define MULT_COEFF_13_B_0 0x825C //602 (CC_LO)
#define MULT_COEFF_13_B_1 0x825D //603 (CC_HI)
#define MULT_COEFF_21_B_0 0x825E //604 (CC_LO)
#define MULT_COEFF_21_B_1 0x825F //605 (CC_HI)
#define MULT_COEFF_22_B_0 0x8260 //606 (CC_LO)
#define MULT_COEFF_22_B_1 0x8261 //607 (CC_HI)
#define MULT_COEFF_23_B_0 0x8262 //608 (CC_LO)
#define MULT_COEFF_23_B_1 0x8263 //609 (CC_HI)
#define MULT_COEFF_31_B_0 0x8264 //610 (CC_LO)
#define MULT_COEFF_31_B_1 0x8265 //611 (CC_HI)
#define MULT_COEFF_32_B_0 0x8266 //612 (CC_LO)
#define MULT_COEFF_32_B_1 0x8267 //613 (CC_HI)
#define MULT_COEFF_33_B_0 0x8268 //614 (CC_LO)
#define MULT_COEFF_33_B_1 0x8269 //615 (CC_HI)
#define MULT_OFFSET1_B 0x826A //616 (CC_LO)
#define MULT_OFFSET2_B 0x826B //617 (CC_HI)
#define MULT_OFFSET3_B 0x826C //618 (CC_LO)
#define DISP_LUT_CTRL 0x8270 //33392 ()
#define POST_LUT_DITHER_CTRL 0x8271 //33393 ()
#define DISP_LUT_DITHER_PRE_FIL 0x8272 //33393 ()
#define DISP_DITHER_ERR_CORECT 0x8274 //33393 ()
// Louis 1104
#define DISP_DITHER_FIL_COEFF 0x8273 //33395 (DP)
#define ADC_FILTER_CONFIG 0x8278
#define ADC_FILTER_DELTA_THRESH 0x8279
#define ADC_FILTER_LOW_THRESH 0x827A
#define ADC_FILTER_HIGH_THRESH 0x827B
#define FLICKER_OFFSET 0x8280 //33408 ()
#define NOFLICKER_OFFSET 0x8281 //33409 ()
#define FLICKER_FRAME_THRESH 0x8282 //33410 ()
#define NOFLICKER_FRAME_THRESH 0x8283 //33411 ()
#define FLICKER_SCORE_MIN_0 0x8284 //33412 ()
#define FLICKER_SCORE_MIN_1 0x8285 //33413 ()
#define FLICKER_SCORE_MIN_2 0x8286 //33414 ()
#define FLICKER_SCORE_MIN FLICKER_SCORE_MIN_0
#define FLICKER_SCORE_0 0x8288 //33416 ()
#define FLICKER_SCORE_1 0x8289 //33417 ()
#define FLICKER_SCORE_2 0x828A //33418 ()
#define VIRTUAL_EDID_CONTROL 0x8290 //33424 ()
#define VIRTUAL_EDID_DATA 0x8291 //33425 ()
#define VIRTUAL_EDID_ADDRESS 0x8292 //33426 ()
#define VIRTUAL_EDID_STATUS 0x8293 //33427 ()
#define MEM_TEST_SIGNATURE_CTRL 0x8294 //33428 ()
#define ROM_TEST_SIG_0 0x8296 //33430 ()
#define ROM_TEST_SIG_1 0x8297 //33431 ()
#define ROM_TEST_SIG_2 0x8298 //33432 ()
#define TEST_CTRL_0 0x82A0
#define ADC_AUTST_LIN_DATA 0x82A9
#define ADC_AUTST_STATUS 0x82AA
#define ADC_AUTST_CTRL 0x82AB
#define ADC_AUTST_SEL 0x82AC
#define ADC_AUTST_HIT 0x82AD
#define CCF_TESTREG 0x82AE //33454 ()
#define RPLL_TEST_CONTROL 0x82AF
#define HDCP_CONTROL 0x82B0 //33456 ()
#define HDCP_ADDR 0x82B1 //33457 ()
#define HDCP_BKSV_0 0x82B2 //33458 ()
#define HDCP_BKSV_1 0x82B3 //33459 ()
#define HDCP_BKSV_2 0x82B4 //33460 ()
#define HDCP_BKSV_3 0x82B5 //33461 ()
#define HDCP_BKSV_4 0x82B6 //33462 ()
#define HDCP_STATUS 0x82B7 //33463 ()
#define DDC2B_CTRL1 0x82B8 //33464 ()
#define DDC2B_CTRL2 0x82B9 //33465 ()
#define DDC2B_STATUS 0x82BA //33466 ()
#define DDC2B_ADDR 0x82BB //33467 ()
#define DDC2B_CLOCK_STATUS 0x82BC //33468 ()
#define DDC2B_DATA 0x82BE //33470 ()
#define RSDS_LVDS_POWER 0x82C0 //33472 ()
#define RSDS_LVDS_DATA_CTRL 0x82C1 //33473 ()
#define LVDS_PLL_CTRL 0x82C2 //33474 ()
#define RSDS_LVDS_MISC1_CTRL 0x82C3 //33475 ()
#define RSDS_LVDS_MISC2_CTRL 0x82C4 //33476 ()
#define CLOCK_SIGNAL_DELAY 0x82C5 //33477 ()
#define RSDS_LVDS_TEST_CTRL 0x82C6 //33478 ()
#define LVDS_TEST_DATA 0x82C7 //33479 ()
#define LVDS_CLK_DATA 0x82C8 //33480 ()
// Reserved 0x82C9
#define TCON_CONTROL1 0x82D0 //33488 ()
#define TCON_CONTROL2 0x82D1 //33489 ()
#define TCON_PANEL_WIDTH_0 0x82D2 //33490 ()
#define TCON_PANEL_WIDTH_1 0x82D3 //33491 ()
#define TCON_SIGNAL_DELAY 0x82D4 //33492 ()
#define TCON_SIGNAL_POLARITY 0x82D6 //33494 ()
#define TCON_SIGNAL_ENABLE 0x82D7 //33495 ()
#define TCON_BLANKING_MASK 0x82D8 //33496 ()
#define ROE_ACTIVE_DELAY 0x82D9 //33497 ()
#define TCON_BLANKING_VSTART_0 0x82DA //33498 ()
#define TCON_BLANKING_VSTART_1 0x82DB //33499 ()
#define TCON_BLANKING_VEND_0 0x82DC //33500 ()
#define TCON_BLANKING_VEND_1 0x82DD //33501 ()
#define TCON_BLANKING_HOFFSET_0 0x82DE //33502 ()
#define TCON_BLANKING_HOFFSET_1 0x82DF //33503 ()
#define LP_HSTART_0 0x82E0 //33504 ()
#define LP_HSTART_1 0x82E1 //33505 ()
#define LP_HEND_0 0x82E2 //33506 ()
#define LP_HEND_1 0x82E3 //33507 ()
#define ESP_HSTART_0 0x82E4 //33508 ()
#define ESP_HSTART_1 0x82E5 //33509 ()
#define ESP_WIDTH 0x82E6 //33510 ()
#define OSP_HSTART_0 0x82E8 //33512 ()
#define OSP_HSTART_1 0x82E9 //33513 ()
#define OSP_WIDTH 0x82EA //33514 ()
#define POL_SWITCH_TIME_0 0x82EC //33516 ()
#define POL_SWITCH_TIME_1 0x82ED //33517 ()
#define ROWCLK_HSTART_0 0x82EE //33518 ()
#define ROWCLK_HSTART_1 0x82EF //33519 ()
#define ROWCLK_HEND_0 0x82F0 //33520 ()
#define ROWCLK_HEND_1 0x82F1 //33521 ()
#define RSP1_VSTART_0 0x82F2 //33522 ()
#define RSP1_VSTART_1 0x82F3 //33523 ()
#define RSP1_WIDTH 0x82F4 //33524 ()
#define POL_INVERSION_LENGTH 0x82F5 //33525 ()
#define ROE1_HSTART_0 0x82F6 //33526 ()
#define ROE1_HSTART_1 0x82F7 //33527 ()
#define ROE1_HEND_0 0x82F8 //33528 ()
#define ROE1_HEND_1 0x82F9 //33529 ()
#define ROE2_HSTART_0 0x82FA //33530 ()
#define ROE2_HSTART_1 0x82FB //33531 ()
#define ROE2_HEND_0 0x82FC //33532 ()
#define ROE2_HEND_1 0x82FD //33533 ()
#define BP0_CTRL 0x8300 //33536 ()
#define BP0_OCM_ADDR_0 0x8302 //33538 ()
#define BP0_OCM_ADDR_1 0x8303 //33539 ()
#define BP0_SUB_ADDR_0 0x8304 //33540 ()
#define BP0_SUB_ADDR_1 0x8305 //33541 ()
#define BP1_CTRL 0x8306 //33542 ()
#define BP1_OCM_ADDR_0 0x8308 //33544 ()
#define BP1_OCM_ADDR_1 0x8309 //33545 ()
#define BP1_SUB_ADDR_0 0x830A //33546 ()
#define BP1_SUB_ADDR_1 0x830B //33547 ()
#define BP2_CTRL 0x830C //33548 ()
#define BP2_OCM_ADDR_0 0x830E //33550 ()
#define BP2_OCM_ADDR_1 0x830F //33551 ()
#define BP2_SUB_ADDR_0 0x8310 //33552 ()
#define BP2_SUB_ADDR_1 0x8311 //33553 ()
#define BP3_CTRL 0x8312 //33554 ()
#define BP3_OCM_ADDR_0 0x8314 //33556 ()
#define BP3_OCM_ADDR_1 0x8315 //33557 ()
#define BP3_SUB_ADDR_0 0x8316 //33558 ()
#define BP3_SUB_ADDR_1 0x8317 //33559 ()
#define TCLK_TMR_CTRL_0 0x83A0 //33696 (OCM)
#define TCLK_TMR_CTRL_1 0x83A1 //33697 (OCM)
#define TCLK_TMR_INT_STATUS 0x83A2 //33698 (OCM)
#define TCLK_TMR_VALUE_0 0x83A4 //33700 (OCM)
#define TCLK_TMR_VALUE_1 0x83A5 //33701 (OCM)
#define TCLK_TMR_COMP_A_0 0x83A6 //33702 (OCM)
#define TCLK_TMR_COMP_A_1 0x83A7 //33703 (OCM)
#define TCLK_TMR_COMP_B_0 0x83A8 //33704 (OCM)
#define TCLK_TMR_COMP_B_1 0x83A9 //33705 (OCM)
#define GPIO_DIRCTRL3 0x83B0 //33712 (HOST)
#define GPINPUT3 0x83B1 //33713 (HOST)
#define GPOUTPUT3 0x83B2 //33714 (HOST)
#define GPIO_DIRCTRL4 0x83B3 //33715 (HOST)
#define GPINPUT4 0x83B4 //33716 (HOST)
#define GPOUTPUT4 0x83B5 //33717 (HOST)
// Louis 1102
#define ADC_CLAMP_CONTROL 0x83C0 //33728 (ADC)
#define ADC_H_CLAMPSTART 0x83C2 //33730 (ADC)
#define ADC_H_CLAMPWIDTH 0x83C3 //33731 (ADC)
#define ADC_V_CLAMPSTART_0 0x83C4 //33732 (ADC)
#define ADC_V_CLAMPSTART_1 0x83C5 //33733 (ADC)
#define ADC_V_CLAMPEND_0 0x83C6 //33734 (ADC)
#define ADC_V_CLAMPEND_1 0x83C7 //33735 (ADC)
#define SYNC_TIP_CLAMP_END 0x83C8 //33736 (ADC)
#define SYNC_TIP_CLAMP_TIME_OUT 0x83C9 //33737 (ADC)
#define LUMA_HIST0 0x83D0 //33744 (CP)
#define LUMA_HIST1 0x83D1 //33745 (CP)
#define LUMA_HIST2 0x83D2 //33746 (CP)
#define LUMA_HIST3 0x83D3 //33747 (CP)
#define LUMA_HIST4 0x83D4 //33748 (CP)
#define LUMA_HIST5 0x83D5 //33749 (CP)
#define LUMA_HIST6 0x83D6 //33750 (CP)
#define LUMA_HIST7 0x83D7 //33751 (CP)
#define LUMA_HIST8 0x83D8 //33752 (CP)
#define LUMA_HIST9 0x83D9 //33753 (CP)
#define LUMA_HIST10 0x83DA //33754 (CP)
#define LUMA_HIST11 0x83DB //33755 (CP)
#define LUMA_HIST12 0x83DC //33756 (CP)
#define LUMA_HIST13 0x83DD //33757 (CP)
#define LUMA_HIST14 0x83DE //33758 (CP)
#define LUMA_HIST15 0x83DF //33759 (CP)
#define ACM_CTRL 0x8806 //43776 (CP)
#define ACM3_INHIBIT_ACC 0x8807 //43777 (CP)
#define ACM_Z1_LUMI_GAIN 0x8800 //43778 (CP)
#define ACM_Z1_LUMI_OFFS 0x8801 //43779 (CP)
#define ACM_Z1_SAT_GAIN 0x8802 //43780 (CP)
#define ACM_Z1_SAT_OFFS 0x8803 //43781 (CP)
#define ACM_Z1_HUE_GAIN 0x8804 //43782 (CP)
#define ACM_Z1_HUE_OFFS 0x8805 //43783 (CP)
#define ACM_Z1_LUMI1 0x8808 //43784 (CP)
#define ACM_Z1_LUMI2 0x8809 //43785 (CP)
#define ACM_Z1_LUMI1_SOFT_0 0x880A //43786 (CP)
#define ACM_Z1_LUMI1_SOFT_1 0x880B //43787 (CP)
#define ACM_Z1_LUMI2_SOFT_0 0x880C //43788 (CP)
#define ACM_Z1_LUMI2_SOFT_1 0x880D //43789 (CP)
#define ACM_Z1_LUMI_FADE 0x880E //43790 (CP)
#define ACM_Z1_SAT_R1 0x8810 //43792 (CP)
#define ACM_Z1_SAT_R2 0x8811 //43793 (CP)
#define ACM_Z1_SATR1_SOFT_0 0x8812 //43794 (CP)
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