📄 register_57xx.h
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/*==========================================================================*/
/*
$Workfile: register_57xx.h $
$Revision: 1.13 $
$Date: Aug 23 2006 23:15:58 $
*/
/****************************************************************************/
/* */
/* Copyright (C) 2004. GENESIS MICROCHIP INC. */
/* All rights reserved. No part of this program may be reproduced. */
/* */
/* Genesis Microchip Inc., 165 Commerce Valley Dr. West */
/* Thornhill, Ontario, Canada, L3T 7V8 */
/* */
/*==========================================================================*/
#ifndef __REGS_H__
#define __REGS_H__
/****************************************************************************/
/* R E G I S T E R D E F I N I T I O N S */
/****************************************************************************/
#define IRAM_OSDSRAMStart 0x00000
#define IRAM_OSDSRAMSize 0x07FFF
#define IRAM_OSDColorLUTStart 0x08400
#define IRAM_OSDColorLUTSize 0x003FF
#define IRAM_ColorControlStart 0x08800
#define IRAM_ColorControlSize 0x007FF
#define IRAM_DisplayGammaLUTStart 0x09000
#define IRAM_DisplayGammaLUTSize 0x00FFF
#define IRAM_HDCPKeyRAMStart 0x0A400
#define IRAM_HDCPKeyRAMSize 0x003FF
#define IRAM_DisplayLineBufferStart 0x10000
#define IRAM_DisplayLineBufferSize 0x07FFF
#if (USE_ACC_ACM || USE_ACM_3D)
// Highlight window must have a minimum Horizontal Front Porch of 27 DCLKs
#define HIGHLIGHT_WINDOW_FRONT_PORCH (27 - 1)
#endif
#define HOST_CONTROL 0x8000 //32768 ()
#define PRODUCT_ID 0x8001 //32769 ()
#define PRODUCT_REV 0x8002 //32770 ()
#define CLOCK_CONFIG 0x8003 //32771 ()
#define OCM_TCLK_DIV 0x8004 //32772 ()
#define BYPASS 0x8006 //32774 ()
#define IRQ_CONFIG 0x800B //32779 ()
#define IFM_OCMMASK 0x800C //32780 ()
#define INPUT_OCMMASK 0x800D //32781 ()
#define MISC_OCMMASK 0x800E //32782 ()
#define SYSTEM_STATUS 0x800F //32783 ()
#define IFM_STATUS 0x8010 //32784 ()
#define INPUT_STATUS 0x8011 //32785 ()
#define DISPLAY_STATUS 0x8012 //32786 ()
#define CLOCK_STATUS 0x8013 //32787 ()
#define MISC_STATUS 0x8014 //32788 ()
#define RCLK_CONFIG 0x8016 //32790 ()
#define RCLK_FREQUENCY 0x8017 //32791 ()
#define RCLK_PLL 0x8018 //32792 ()
#define FCLK_FREQ_0 0x801A //32794 ()
#define FCLK_FREQ_1 0x801B //32795 ()
#define FCLK_FREQ FCLK_FREQ_0
#define LCLK_FREQ_0 0x801C //32796 ()
#define LCLK_FREQ_1 0x801D //32797 ()
#define LCLK_FREQ LCLK_FREQ_0
#define OCM_BUS_CONTROL 0x8020 //32800 ()
#define OCM_WBUF_STATUS 0x8021 //32801 ()
#define OCM_BUS_WDT_INIT 0x8022 //32802 ()
#define OCM_BUS_WDT_STATUS 0x8023 //32803 ()
#define OCM_WDT_ERR_ADDR_0 0x8024 //32804 ()
#define OCM_WDT_ERR_ADDR_1 0x8025 //32805 ()
#define OCM_WDT_ERR_ADDR_2 0x8026 //32806 ()
#define OCM_CONTROL 0x8027 //32807 ()
#define SPI_CONTROL 0x802A //32810 ()
#define SPI_STATUS 0x802B //32811 ()
#define SPI_DATA_0 0x802C //32812 ()
#define SPI_DATA_1 0x802D //32813 ()
#define SPI_CACHE_CTRL 0x802E //32814 ()
#define PWM0_CONFIG 0x8030 //32816 ()
#define PWM0_PERIOD 0x8031 //32817 ()
#define PWM0_PULSE 0x8032 //32818 ()
#define PWM1_CONFIG 0x8033 //32819 ()
#define PWM1_PERIOD 0x8034 //32820 ()
#define PWM1_PULSE 0x8035 //32821 ()
#define GPIO_DIRCTRL1 0x803C //32828 ()
#define GPO_OPENDRAIN_EN1 0x803D //32829 ()
#define GPINPUT1 0x803E //32830 ()
#define GPOUTPUT1 0x803F //32831 ()
#define GPO_OUTPUT 0x8040 //32832 ()
#define GPO_OPENDRAIN_EN 0x8041 //32833 ()
#define GPINPUT 0x8042 //32834 ()
#define LOW_BW_ADC_CTRL 0x8048 //32840 ()
#define LOW_BW_ADC_RESULT 0x8049 //32841 ()
#define LOW_BW_ADC_STATUS 0x804A //32842 ()
#define LOW_BW_ADC_TEST 0x804B
// Louis 1104
#define LBADC_OUT_EN 0x804C //32844 (HOST)
#define POWER_STATUS 0x804D //32845 (HOST)
#define AOC_CTRL0 0x8050 //32848 (ADC)
#define AOC_CTRL1 0x8051 //32849 (ADC)
#define AOC_SAMPLE_PER_LINE 0x8052 //32850 (ADC)
#define AOC_REFERENCE 0x8053 //32851 (ADC)
#define VPORT_CTRL 0x810A
//Power_Status
#define BROWN_OUT_30 0
#define BROWN_OUT_27 1
// AOC_CTRL (0x8050)
#define AOC_EN BIT0
#define AOC_DONT_UPDATE BIT1
// phyang 01/26/06: 9-bit Offset1.
#define ADC_RED_GRN_OFFSET1_LSB 0x805E
#define ADC_BLU_OFFSET1_LSB 0x805F
#define ADC_CONTROL 0x8060 //32864 ()
#define ADC_RESERVED_0 0x8061 //32865 ()
#define ADC_RESERVED_1 0x8062 //32866 ()
#define ADC_SYNC_LEVEL 0x8063 //32867 ()
#define ADC_FAS1 0x8064 //32868 ()
#define ADC_FAS2 0x8065 //32869 ()
#define ADC_TEST1 0x8066 //32870 ()
#define ADC_TEST2 0x8067 //32871 ()
#define ADC_DATA_RED 0x8068 //32872 ()
#define ADC_DATA_GRN 0x8069 //32873 ()
#define ADC_DATA_BLU 0x806A //32874 ()
#define ADC_FLAGS 0x806B //32875 ()
#define RED_OFFSET1 0x806C //32876 ()
#define RED_OFFSET2 0x806D //32877 ()
#define RED_GAIN_0 0x806E //32878 ()
#define RED_GAIN_1 0x806F //32879 ()
#define RED_GAIN RED_GAIN_0
#define GRN_OFFSET1 0x8070 //32880 ()
#define GRN_OFFSET2 0x8071 //32881 ()
#define GRN_GAIN_0 0x8072 //32882 ()
#define GRN_GAIN_1 0x8073 //32883 ()
#define GRN_GAIN GRN_GAIN_0
#define BLU_OFFSET1 0x8074 //32884 ()
#define BLU_OFFSET2 0x8075 //32885 ()
#define BLU_GAIN_0 0x8076 //32886 ()
#define BLU_GAIN_1 0x8077 //32887 ()
#define BLU_GAIN BLU_GAIN_0
#define ADC_TESTDAC 0x8078 //32888 ()
#define ADC_DAC_DATA 0x8079 //32889 ()
#define ADC_MODULATION 0x807A //32890 ()
#define MISSING_CODE_TEST 0x807B //32891 ()
#define ADC_RG_PHASE 0x807C //32892 ()
#define ADC_B_PHASE 0x807D //32893 ()
// Louis 1103
//#define SYNC_TIP_CLAMP_END 0x807E //32894 ()
//#define SYNC_TIP_CLAMP_TIME_OUT 0x807F //32895 ()
#define DVI_CTRL 0x8080 //32896 ()
#define DVI_EQUALIZATION 0x8081 //32897 ()
#define DVI_CONFIG 0x8082 //32898 ()
#define DVI_DE 0x8083 //32899 ()
#define DVI_PLL 0x8084 //32900 ()
#define DVI_MISC 0x8088 //32904 ()
#define DVI_TESTCTRL 0x8089
#define DVI_TEST 0x808A
#define DVI_PHASE_ADJ 0x808B
#define DVI_SIGQUAL_0 0x808C //32908 ()
#define DVI_SIGQUAL_1 0x808D //32909 ()
#define DVI_SIGQUAL_2 0x808E //32910 ()
#define DVI_SIGQUAL DVI_SIGQUAL_0
#define DVI_RCAL_RESULT 0x809C //32924 ()
#define DVI_DE_WIDTH_CLAMP_0 0x809E //32926 ()
#define DVI_DE_WIDTH_CLAMP_1 0x809F //32927 ()
#define DVI_DE_WIDTH_CLAMP DVI_DE_WIDTH_CLAMP_0
#define IP_CONTROL 0x80A0 //32928 ()
#define IP_POLARITY 0x80A1 //32929 ()
#define CSYNC_CONTROL 0x80A3 //32931 ()
#define COAST_START_0 0x80A4 //32932 ()
#define COAST_START_1 0x80A5 //32933 ()
#define COAST_START COAST_START_0
#define COAST_END_0 0x80A6 //32934 ()
#define COAST_END_1 0x80A7 //32935 ()
#define COAST_END COAST_END_0
#define IPHS_DELAY_0 0x80A8 //32936 ()
#define IPHS_DELAY_1 0x80A9 //32937 ()
#define IPHS_DELAY IPHS_DELAY_0
#define IPVS_DELAY_0 0x80AA //32938 ()
#define IPVS_DELAY_1 0x80AB //32939 ()
#define IPVS_DELAY IPVS_DELAY_0
#define IPH_ACT_START_0 0x80AC //32940 ()
#define IPH_ACT_START_1 0x80AD //32941 ()
#define IPH_ACT_START IPH_ACT_START_0
#define IPH_ACT_WIDTH_0 0x80AE //32942 ()
#define IPH_ACT_WIDTH_1 0x80AF //32943 ()
#define IPH_ACT_WIDTH IPH_ACT_WIDTH_0
#define IPV_ACT_START_ODD_0 0x80B0 //32944 ()
#define IPV_ACT_START_ODD_1 0x80B1 //32945 ()
#define IPV_ACT_START_ODD IPV_ACT_START_ODD_0
#define IPV_ACT_START_EVEN_0 0x80B2 //32946 ()
#define IPV_ACT_START_EVEN_1 0x80B3 //32947 ()
#define IPV_ACT_START_EVEN IPV_ACT_START_EVEN_0
#define IPV_ACT_LENGTH_0 0x80B4 //32948 ()
#define IPV_ACT_LENGTH_1 0x80B5 //32949 ()
#define IPV_ACT_LENGTH IPV_ACT_LENGTH_0
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