📄 52xx_panel.h
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#define Panel_Invert_DCLK 0x00 //0x01
#define Panel_Invert_DEN 0x00
#define PanelPadDrive 0x555555UL
// Define panel power up/down timing. WORD constant used to program registers 0x1D8 and 0x1D9 during power up and power down
//for TCLK=14.318MHz, 1Tick = TCLK/511/32 = 1.14ms.
#define PowerUpPanelTiming 0x2baf //T1 = 50ms, T2 = 200ms;
#define PowerDownPanelTiming 0xaf2b //note, this can be different for power down
// For correct power down sequence.
#define PowerDownTimeIn10ms 20 //from powerDownSequence enable to data Hiz, PDR#2840, 2884
#define PanelSpreadSpectrumCtrl 0x0 // Value for Spread_Spectrum_Control register
// If LVDS, spread spectrum control is always disabled.
#ifdef LVDS_PANEL
#define Panel_Spread_Spect_En 0x00 // 0x01 : Enable spectrum, 0x00 : Disable spectrum
#define Panel_LVDS_BusType 0x00 //0x00: single bus; 0x01: dual bus
#else
#define Panel_Spread_Spect_En 0x01 // 0x01 : Enable spectrum, 0x00 : Disable spectrum
#endif
// Added to compliment the PanelPadDrive
#define PanelDClkDelay 0 // DCLK display timing delay adjustment in ns unit.
#define Panel_LVDSBus_EvenOddSwap 0x00 //0x01 - Swap 0x00 NoSwap
#endif //LG_WXGA_17132P3M08016 panel
#if PANEL == Hitachi_TX38D85VC1CAJ // Added for Sony VAIO panel
#define LVDS_PANEL // LVDS panel
#define PanelName "Hitachi_TX38D85VC1CAJ"
#define PanelTwoPixelPerClk 0 // Single pixel output
#define PanelDepth 6
#define PanelWidth 1024
#define PanelHeight 768
#define PanelMaxVFreq 76 // Hz
#define PanelMinVFreq 1 // Hz
#define PanelMaxHFreq 68900 // Hz
#define PanelMaxPClk 80000UL // KHz
#define PanelMinHTotal 1142
#define PanelMinHSyncFrontPorch 10
#define PanelMinHSyncWidth 32
#define PanelMinHSyncBackPorch 32
#define PanelHActiveStart (PanelMinHSyncWidth + PanelMinHSyncBackPorch)
#define PanelHActiveEnd (PanelHActiveStart + PanelWidth)
#define PanelMaxVTotal 1000
#define PanelTypVTotal 806
#define PanelMinVTotal 776
#define PanelMinVSyncFrontPorch 1
#define PanelMinVSyncWidth 2
#define PanelMinVSyncBackPorch 4
#define PanelVActiveStart (PanelMinVSyncWidth + PanelMinVSyncBackPorch)
#define PanelVActiveEnd (PanelVActiveStart + PanelHeight)
#define Panel_Invert_DVS 0x01
#define Panel_Invert_DHS 0x01
#define Panel_Invert_DCLK 0x01
#define Panel_Invert_DEN 0x00
#define PanelPadDrive 0x775533UL
// Define panel power up/down timing. WORD constant used to program registers 0x1D8 and 0x1D9 during power up and power down
// other parameters. gWizard will change the output data as well.
#define PowerUpPanelTiming 0x9944
#define PowerDownPanelTiming 0x9944 // note, this can be different for power down
// For correct power down sequence.
#define PowerDownTimeIn10ms 20 //from powerDownSequence enable to data Hiz, PDR#2840, 2884
#define PanelSpreadSpectrumCtrl 0x0f // Value for Spread_Spectrum_Control register
// If LVDS, spread spectrum control is always disabled.
#ifdef LVDS_PANEL
#define Panel_Spread_Spect_En 0x00 // 0x01 : Enable spectrum, 0x00 : Disable spectrum
#define Panel_LVDS_BusType 0x00 //0x00: single bus; 0x01: dual bus
#else
#define Panel_Spread_Spect_En 0x01 // 0x01 : Enable spectrum, 0x00 : Disable spectrum
#endif
// Added to compliment the PanelPadDrive
#define PanelDClkDelay 0 // DCLK display timing delay adjustment in ns unit.
#define Panel_LVDSBus_EvenOddSwap 0x00 //0x01 - Swap 0x00 NoSwap
#endif
//RSDS panels
#if PANEL == AU_M170ES05_LTU170ES05E
#define PanelName "AU_M170ES05_LTU170ES05E"
#define RSDS_PANEL
// Removed PanelXga, PanelSxga, and PanelUxga parameters.
#define PanelTwoPixelPerClk 0 // Single pixel output
#define PanelDepth 6
#define PanelWidth 1280
#define PanelHeight 1024
#define PanelMaxVFreq 77 // Hz
#define PanelMinVFreq 50 // Hz
#define PanelMaxHFreq 70000 // Hz
#define PanelMaxPClk 138000UL // KHz
// Added for general purpose.
#define PanelTypHTotal 1688
#define PanelMinHTotal 1620 //1600 //Sandhya
#define PanelMinHSyncWidth 120
#define PanelMinHSyncFrontPorch 10 //Sandhya
#define PanelMinHSyncBackPorch 200
#define PanelHActiveStart PanelMinHSyncWidth + PanelMinHSyncBackPorch
#define PanelHActiveEnd PanelHActiveStart + PanelWidth
#define PanelMaxVTotal 1300
#define PanelTypVTotal 1066
#define PanelMinVTotal 1034 //1032
#define PanelMinVSyncWidth 3
#define PanelMinVSyncFrontPorch 1 //Sandhya
#define PanelMinVSyncBackPorch 6
#define PanelVActiveStart PanelMinVSyncWidth + PanelMinVSyncBackPorch
#define PanelVActiveEnd PanelVActiveStart + PanelHeight
#define PanelVBlankRangeStart PanelHeight
#define PanelVBlankRangeEnd PanelVBlankRangeStart + 30
// Corrected to use appropriate DDDS divider values for SXGA panel.
#define FreeRunPllDiv 0xCC
#define FreeRunClkDiv 0x09
#define Panel_Invert_DVS 0xFF
#define Panel_Invert_DHS 0xFF
#define Panel_Invert_DCLK 0x00
#define Panel_Invert_DEN 0x00
#define INTERLACED_FIELD_LENGTH 20
#define PanelPadDrive 0x775522UL
#define Panel_LVDS_BusType 0x01 //0x00: single bus; 0x01: dual bus
// Define panel power up/down timing.
#define PowerUpPanelTiming 0xaf57 //0xC208 //PDR:7992
#define PowerDownPanelTiming 0x57af //0xC208 //PDR:7992
// For correct power down sequence.
#define PowerDownTimeIn10ms 33 // From powerDownSequence enable to data Hiz, PDR#2840, 2884
#define PanelSpreadSpectrumCtrl 0xFF //0x00 PDR:7317 - 10Feb04 zan3SR related changes // Value for Spread_Spectrum_Control register
#define Panel_Spread_Spect_En 0xFF //0x00 - PDR:7317 - 10Feb04 zan3SR related changes
// 0xFF : enable spectrum
// 0x00 : disable spectrum
// Added to compliment the PanelPadDrive
#define PanelDClkDelay 0 // DCLK display timing delay adjustment in ns unit.
/************************************************************************/
//RSDS specific parameters
//#define RsdsLvdsPower LVDS_EN | LVDS_CH3_EN | LVDS_PLL_EN | OUTPUT_DRIVE_EVEN_EN | OUTPUT_DRIVE_ODD_EN | MLR_BIAS_EN //0x9f
#define RsdsLvdsPower LVDS_CH3_EN | LVDS_PLL_EN | OUTPUT_DRIVE_EVEN_EN | OUTPUT_DRIVE_ODD_EN | MLR_BIAS_EN //0x1f
//#define RsdsLvdsDataCtrl DUAL_BUS_EN | EVEN_ODD_SWAP | POS_NEG_SWAP | EIGHT_BIT_MODE_SEL //0x2b
#define RsdsLvdsDataCtrl (DUAL_BUS_EN|LSB_MSB_SWAP| POS_NEG_SWAP) // 0x89
#define LvdsPLLCtrl 0x0
#define RsdsLvdsMisc1Ctrl 0x02
#define RsdsLvdsMisc2Ctrl 0x04
#define ClockSignalDelay 0x88
#define RsdsLvdsTestCtrl 0
#define LvdsTestData 0
#define LvdsClkData 0x0
/*
#define RsdsLvdsPower (OUTPUT_DRIVE_EVEN_EN | LVDS_PLL_EN | MLR_BIAS_EN | LVDS_CH3_EN | OUTPUT_DRIVE_ODD_EN) //0x0e4
#define RsdsLvdsDataCtrl (LSB_MSB_SWAP | POS_NEG_SWAP | Panel_LVDS_BusType) //0x0e5
#define LvdsPLLCtrl 0x00 //0x0e6
#define RsdsLvdsMisc1Ctrl TCON_CLK_INV //0x0e7
#define RsdsLvdsMisc2Ctrl BIT_ORDER_SWAP //0x0e8
#define ClockSignalDelay 0x33 //bits 0:3 is ECLK delay, bits 4:7 is OCLK delay
#define RsdsLvdsTestCtrl 0x00 //0x0ea
#define LvdsTestData 0x00 //0x0eb
#define LvdsClkData 0x61 //0x0ec
*/
/************************************************************************/
// TCON Specific Parameters
#define Use_TCON 1
#define TConCtrl1 0x02
#define TConCtrl2 0x01
#define TConPanelWidth 0x500
#define TConSignalDelay1 0x70//0x00
#define TConSignalDelay2 0x00
#define TConSignalPolarity 0x60
#define TConSignalEnable 0x7f
//TCON Signals Timing Controls
#define TConBlankingMask 0x00
#define TConROEActiveDelay 0x00
#define TConBlankingVStart 0x00
#define TConBlankingVEnd 0x05 // #PDR 9545, Resolve Vertical bar iseeue.
#define TConBlankingHOffset 0x00
#define TConLpHStart 0x2b0 // LP_HSTART Hi/Lo
#define TConLpHEnd 0x2c8 // LP_HEND Hi/Lo
#define TConESPHStart 0x3dd
#define TConESPWidth 0x02
#define TConOSPHStart 0x3da
#define TConOSPWidth 0x02
#define TConPolSwitchTime 0x2ad // POL_SWITCH_TIME Hi/Lo
#define TConRowClkHStart 0x208 // ROWCLK_HSTART Hi/Lo
#define TConRowClkHEnd 0x2c8 // ROWCLK_HEND Hi/Lo
#define TConRSP1VStart 0x0a // RSP1_VSTART Hi/Lo
#define TConRSP1Width 0x01 // RSP1 width
#define TConRSP2VStart 0x00 // RSP2_VSTART Hi/Lo
#define TConRSP2Width 0x00 // RSP2 width
#define TConROE1HStart 0x1e8 // ROE1_HSTART Hi/Lo
#define TConROE1HEnd 0x2c8 // ROE1_HEND Hi/Lo
#define TConROE2HStart 0x0 // ROE2_HSTART Hi/Lo
#define TConROE2HEnd 0x0 // ROE2_HEND Hi/Lo
#define TConROE3HStart 0x0 // ROE3_HSTART Hi/Lo
#define TConROE3HEnd 0x0 // ROE3_HEND Hi/Lo
/************************************************************************/
// 13May04 - zan3S related changes - panel flicker dection
//Panel flicker detection block parameters
#define EnableFlickerDetection 1 //1 - enable, 0 - disable panel flicker detection
#define FlickerOffset 32 //0x0d2
#define NoFlickerOffset 24 //0x0d3
#define FlickerFrameThresh 5 //0x0d4
#define NoFlickerFrameThresh 5 //0x0d5
#define NoFlickerFrameThresh 5 //0x0d5
/************************************************************************/
#endif // #if PANEL == AU_M170ES05_LTU170ES05E
#if PANEL == AU_M170ES05_LTU170ES05FD
#define PanelName "AU_M170ES05_LTU170ES05FD"
#define RSDS_PANEL
// Removed PanelXga, PanelSxga, and PanelUxga parameters.
#define PanelTwoPixelPerClk 0 // Single pixel output
#define PanelDepth 6
#define PanelWidth 1280
#define PanelHeight 1024
#define PanelMaxVFreq 77 // Hz
#define PanelMinVFreq 50 // Hz
#define PanelMaxHFreq 70000 // Hz
#define PanelMaxPClk 138000UL // KHz
// Added for general purpose.
#define PanelTypHTotal 1688
#define PanelMinHTotal 1620 //1600 //Sandhya
#define PanelMinHSyncWidth 120
#define PanelMinHSyncFrontPorch 10 //Sandhya
#define PanelMinHSyncBackPorch 200
#define PanelHActiveStart PanelMinHSyncWidth + PanelMinHSyncBackPorch
#define PanelHActiveEnd PanelHActiveStart + PanelWidth
#define PanelMaxVTotal 1300
#define PanelTypVTotal 1066
#define PanelMinVTotal 1034 //1032
#define PanelMinVSyncWidth 3
#define PanelMinVSyncFrontPorch 1 //Sandhya
#define PanelMinVSyncBackPorch 6
#define PanelVActiveStart PanelMinVSyncWidth + PanelMinVSyncBackPorch
#define PanelVActiveEnd PanelVActiveStart + PanelHeight
#define PanelVBlankRangeStart PanelHeight
#define PanelVBlankRangeEnd PanelVBlankRangeStart + 30
// Corrected to use appropriate DDDS divider values for SXGA panel.
#define FreeRunPllDiv 0xCC
#define FreeRunClkDiv 0x09
#define Panel_Invert_DVS 0xFF
#define Panel_Invert_DHS 0xFF
#define Panel_Invert_DCLK 0x00
#define Panel_Invert_DEN 0x00
#define INTERLACED_FIELD_LENGTH 20
#define PanelPadDrive 0x775522UL
#define Panel_LVDS_BusType 0x01 //0x00: single bus; 0x01: dual bus
// Define panel power up/down timing.
#define PowerUpPanelTiming 0xaf57 //0xC208 //PDR:7992
#define PowerDownPanelTiming 0x57af //0xC208 //PDR:7992
// For correct power down sequence.
#define PowerDownTimeIn10ms 33 // From powerDownSequence enable to data Hiz, PDR#2840, 2884
#define PanelSpreadSpectrumCtrl 0xFF //0x00 PDR:7317 - 10Feb04 zan3SR related changes // Value for Spread_Spectrum_Control register
#define Panel_Spread_Spect_En 0xFF //0x00 - PDR:7317 - 10Feb04 zan3SR related changes
// 0xFF : enable spectrum
// 0x00 : disable spectrum
// Added to compliment the PanelPadDrive
#define PanelDClkDelay 0 // DCLK display timing delay adjustment in ns unit.
/************************************************************************/
//RSDS specific parameters
//#define RsdsLvdsPower LVDS_EN | LVDS_CH3_EN | LVDS_PLL_EN | OUTPUT_DRIVE_EVEN_EN | OUTPUT_DRIVE_ODD_EN | MLR_BIAS_EN //0x9f
#define RsdsLvdsPower LVDS_CH3_EN | LVDS_PLL_EN | OUTPUT_DRIVE_EVEN_EN | OUTPUT_DRIVE_ODD_EN | MLR_BIAS_EN //0x1f
//#define RsdsLvdsDataCtrl DUAL_BUS_EN | EVEN_ODD_SWAP | POS_NEG_SWAP | EIGHT_BIT_MODE_SEL //0x2b
#define RsdsLvdsDataCtrl (DUAL_BUS_EN | POS_NEG_SWAP | LSB_MSB_SWAP) // 0x89
#define LvdsPLLCtrl 0x0
#define RsdsLvdsMisc1Ctrl 0x02
#define RsdsLvdsMisc2Ctrl 0x04
#define ClockSignalDelay 0x88
#define RsdsLvdsTestCtrl 0
#define LvdsTestData 0
#define LvdsClkData 0x0
/*
#define RsdsLvdsPower (OUTPUT_DRIVE_EVEN_EN | LVDS_PLL_EN | MLR_BIAS_EN | LVDS_CH3_EN | OUTPUT_DRIVE_ODD_EN) //0x0e4
#define RsdsLvdsDataCtrl (LSB_MSB_SWAP | POS_NEG_SWAP | Panel_LVDS_BusType) //0x0e5
#define LvdsPLLCtrl 0x00 //0x0e6
#define RsdsLvdsMisc1Ctrl TCON_CLK_INV //0x0e7
#define RsdsLvdsMisc2Ctrl BIT_ORDER_SWAP //0x0e8
#define ClockSignalDelay 0x33 //bits 0:3 is ECLK delay, bits 4:7 is OCLK delay
#define RsdsLvdsTestCtrl 0x00 //0x0ea
#define LvdsTestData 0x00 //0x0eb
#define LvdsClkData 0x61 //0x0ec
*/
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