📄 57xx_config.h
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/*
$Workfile: 57xx_config.h $
$Revision: 1.6 $
$Date: May 25 2006 01:01:36 $
*/
//******************************************************************
//
// Copyright (C) 2002. GENESIS MICROCHIP INC.
// All rights reserved. No part of this program may be reproduced
//
// Genesis Microchip Corp., 2150 Gold Street
// Alviso, CA 95002 USA
// Genesis Microchip Inc., 165 Commerce Valley Dr. West
// Thornhill, Ontario, Canada, L3T 7V8
//
//================================================================
//
// MODULE: 52xx-config.h
//
// USAGE : Header file that defines user option.
//
//******************************************************************
#ifndef _PHOENIX_CONFIG_H_
#define _PHOENIX_CONFIG_H_
#define SOG_SENSITIVITY 0x01
#ifdef __EV_BD_57XX__
/******************************************************************************************/
#define USE_AUDIO 0 //include code to address Audio port. /
#define USE_VPORT 0 // include code to address VPORT. /
#define USE_GSEL_DRVR_MODEL 0 // include code to support GSEL drivers /
#define USE_COMPONENT_INPUT_ON_RGB 0 // include Componenet Port on RGB /
/******************************************************************************************/
#elif defined(__RD1_57XX__)
/******************************************************************************************/
#define USE_AUDIO 0 //include code to address Audio port. /
#define USE_VPORT 0 // include code to address VPORT. /
#define USE_GSEL_DRVR_MODEL 0 // include code to support GSEL drivers /
#define USE_COMPONENT_INPUT_ON_RGB 0 // include Componenet Port on RGB /
/******************************************************************************************/
#elif defined(__RD3_57XX__)
/******************************************************************************************/
#define USE_AUDIO 1 //include code to address Audio port. /
#define USE_VPORT 1 // include code to address VPORT. /
#define USE_GSEL_DRVR_MODEL 1 // include code to support GSEL drivers /
#define USE_COMPONENT_INPUT_ON_RGB 1 // include Componenet Port on RGB /
/******************************************************************************************/
#elif defined(__EV_BD_B_57XX__)
/******************************************************************************************/
#define USE_AUDIO 1 //include code to address Audio port. /
#define USE_VPORT 1 // include code to address VPORT. /
#define USE_GSEL_DRVR_MODEL 1 // include code to support GSEL drivers /
#define USE_COMPONENT_INPUT_ON_RGB 1 // include Componenet Port on RGB /
/******************************************************************************************/
#else
/******************************************************************************************/
#define USE_AUDIO 0 //include code to address Audio port. /
#define USE_VPORT 0 // include code to address VPORT. /
#define USE_GSEL_DRVR_MODEL 0 // include code to support GSEL drivers /
#define USE_COMPONENT_INPUT_ON_RGB 0 // include Componenet Port on RGB /
/******************************************************************************************/
#endif
#define SKIP_VIDEO_PORT_SCAN_IN_PWERDOWM_MODE 1 // if 1 but SkipAutoScan=0, CVBS, SVIDEO, COMPONENT ports
// will be scaned in normal operation mode.
// But Won't be scaned in power saving mode
#define POWER_DOWN_VID_IN_POWER_SAVING 1 // Turn off Video Decoder Power in Power Saving mode.
// Otherwise, Video Decoder will just enter s/w power
// saving mode.
#define USE_VIDEO_FEATURES 0 // vcr ff/rew adjust etc.
#define USE_ACC_ACM 1 // 3-Bin ACC/ACM
#define USE_ACM_3D 1 //enable ACM-3D
#define ACM_ZONE1_START 0x8800 //ACM-3D zone1 start register address
#define USE_LED_BLINK_NO_SYNC 1
/**************************************************************************/
/* C H I P S P E C I F I C C O N S T A N T S */
/**************************************************************************/
// (PanelMinHTotal - PanelWidth) > 53
// Display horizontal timing has a blanking time of 54 DCLKs minimum
#define DISPLAY_HORIZONTAL_BLANKING_MIN (54 - 1)
#define DV_TOTAL_MAX_VALUE 0x0FFF // reg. DV_TOTAL is 12 bits wide.
// Merlin 0830-1
#define ADC_SYNC_L_H_THRSH_VAL 1 // 0)1.9V, 1)2.0V
#define ADC_SYNC_H_L_THRSH_VAL 1 // 0)0.9V, 1)0.8V
#define TOPOSDMEM 0x4000
#endif// _PHOENIX_CONFIG_H_
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