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<!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN"><HTML><HEAD><TITLE>80386 Programmer's Reference Manual -- Section 9.6</TITLE></HEAD><BODY><B>up:</B> <A HREF="c09.htm">Chapter 9 -- Exceptions and Interrupts</A><BR><B>prev:</B> <A HREF="s09_05.htm">9.5 IDT Descriptors</A><BR><B>next:</B> <A HREF="s09_07.htm">9.7 Error Code</A><P><HR><P><H1>9.6 Interrupt Tasks and Interrupt Procedures</H1>Just as a <A HREF="CALL.htm">CALL</A> instruction can call either a procedure or a task, so aninterrupt or exception can "call" an interrupt handler that is either aprocedure or a task. When responding to an interrupt or exception, theprocessor uses the interrupt or exception identifier to index a descriptorin the IDT. If the processor indexes to an interrupt gate or trap gate, itinvokes the handler in a manner similar to a <A HREF="CALL.htm">CALL</A> to a call gate. If theprocessor finds a task gate, it causes a task switch in a manner similar toa <A HREF="CALL.htm">CALL</A> to a task gate.<H2>9.6.1 Interrupt Procedures</H2>An interrupt gate or trap gate points indirectly to a procedure which willexecute in the context of the currently executing task as illustrated by<A HREF="#fig9-4">Figure 9-4</A> . The selector of the gate points to an executable-segmentdescriptor in either the GDT or the current LDT. The offset field of thegate points to the beginning of the interrupt or exception handlingprocedure.<P>The 80386 invokes an interrupt or exception handling procedure in much thesame manner as it <A HREF="CALL.htm">CALL</A>s a procedure; the differences are explained in thefollowing sections.<P><A NAME="fig9-4"><IMG align=center SRC="fig9-4.gif" border=0><H3>9.6.1.1 Stack of Interrupt Procedure</H3>Just as with a control transfer due to a <A HREF="CALL.htm">CALL</A> instruction, a controltransfer to an interrupt or exception handling procedure uses the stack tostore the information needed for returning to the original procedure. As<A HREF="#fig9-5">Figure 9-5</A> shows, an interrupt pushes the EFLAGS register onto the stackbefore the pointer to the interrupted instruction.<P>Certain types of exceptions also cause an error code to be pushed on thestack. An exception handler can use the error code to help diagnose theexception.<H3>9.6.1.2 Returning from an Interrupt Procedure</H3>An interrupt procedure also differs from a normal procedure in the methodof leaving the procedure. The <A HREF="IRET.htm">IRET</A> instruction is used to exit from aninterrupt procedure. <A HREF="IRET.htm">IRET</A> is similar to <A HREF="RET.htm">RET</A> except that <A HREF="IRET.htm">IRET</A> increments EIPby an extra four bytes (because of the flags on the stack) and moves thesaved flags into the EFLAGS register. The IOPL field of EFLAGS is changedonly if the CPL is zero. The IF flag is changed only if CPL <= IOPL.<P><A NAME="fig9-5"><IMG align=center SRC="fig9-5.gif" border=0><H3>9.6.1.3 Flags Usage by Interrupt Procedure</H3>Interrupts that vector through either interrupt gates or trap gates causeTF (the trap flag) to be reset after the current value of TF is saved on thestack as part of EFLAGS. By this action the processor prevents debuggingactivity that uses single-stepping from affecting interrupt response. Asubsequent <A HREF="IRET.htm">IRET</A> instruction restores TF to the value in the EFLAGS image onthe stack.<P>The difference between an interrupt gate and a trap gate is in the effecton IF (the interrupt-enable flag). An interrupt that vectors through aninterrupt gate resets IF, thereby preventing other interrupts frominterfering with the current interrupt handler. A subsequent<A HREF="IRET.htm">IRET</A> instruction restores IF to the value in the EFLAGS image on the stack. Aninterrupt through a trap gate does not change IF.<H3>9.6.1.4 Protection in Interrupt Procedures</H3>The privilege rule that governs interrupt procedures is similar to that forprocedure calls: the CPU does not permit an interrupt to transfer control toa procedure in a segment of lesser privilege (numerically greater privilegelevel) than the current privilege level. An attempt to violate this ruleresults in a general protection exception.<P>Because occurrence of interrupts is not generally predictable, thisprivilege rule effectively imposes restrictions on the privilege levels atwhich interrupt and exception handling procedures can execute. Either of thefollowing strategies can be employed to ensure that the privilege rule isnever violated.<UL><LI> Place the handler in a conforming segment. This strategy suits thehandlers for certain exceptions (divide error, for example). Such ahandler must use only the data available to it from the stack. If itneeded data from a data segment, the data segment would have to haveprivilege level three, thereby making it unprotected.<LI> Place the handler procedure in a privilege level zero segment.</UL><P><H2>9.6.2 Interrupt Tasks</H2>A task gate in the IDT points indirectly to a task, as <A HREF="#fig9-6">Figure 9-6</A>illustrates. The selector of the gate points to a TSS descriptor in the GDT.<P>When an interrupt or exception vectors to a task gate in the IDT, a taskswitch results. Handling an interrupt with a separate task offers twoadvantages:<UL><LI> The entire context is saved automatically.<LI> The interrupt handler can be isolated from other tasks by giving it aseparate address space, either via its LDT or via its page directory.</UL>The actions that the processor takes to perform a task switch are discussedin <A HREF="c07.htm">Chapter 7</A>. The interrupt task returns to the interrupted task byexecuting an <A HREF="IRET.htm">IRET</A> instruction.<P>If the task switch is caused by an exception that has an error code, theprocessor automatically pushes the error code onto the stack thatcorresponds to the privilege level of the first instruction to be executedin the interrupt task.<P>When interrupt tasks are used in an operating system for the 80386, thereare actually two schedulers: the software scheduler (part of the operatingsystem) and the hardware scheduler (part of the processor's interruptmechanism). The design of the software scheduler should account for the factthat the hardware scheduler may dispatch an interrupt task wheneverinterrupts are enabled.<P><A NAME="fig9-6"><IMG align=center SRC="fig9-6.gif" border=0><P><HR><P><B>up:</B> <A HREF="c09.htm">Chapter 9 -- Exceptions and Interrupts</A><BR><B>prev:</B> <A HREF="s09_05.htm">9.5 IDT Descriptors</A><BR><B>next:</B> <A HREF="s09_07.htm">9.7 Error Code</A></BODY>⌨️ 快捷键说明
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