s09_08.htm

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</A>
<H2>9.8.11 Interrupt 11 -- Segment Not Present</H2>
Exception 11 occurs when the processor detects that the present bit of a
descriptor is zero. The processor can trigger this fault in any of these
cases:
<UL>
<LI> While attempting to load the CS, DS, ES, FS, or GS registers; loading
the SS register, however, causes a stack fault.
<LI> While attempting loading the LDT register with an 
<A HREF="LLDT.htm">LLDT</A> instruction;
loading the LDT register during a task switch operation, however,
causes the "invalid TSS" exception.
<LI> While attempting to use a gate descriptor that is marked not-present.
</UL>
This fault is restartable. If the exception handler makes the segment
present and returns, the interrupted program will resume execution.
<P>
If a not-present exception occurs during a task switch, not all the steps
of the task switch are complete. During a task switch, the processor first
loads all the segment registers, then checks their contents for validity. If
a not-present exception is discovered, the remaining segment registers have
not been checked and therefore may not be usable for referencing memory. The
not-present handler should not rely on being able to use the values found
in CS, SS, DS, ES, FS, and GS without causing another exception. The
exception handler should check all segment registers before trying to resume
the new task; otherwise, general protection faults may result later under
conditions that make diagnosis more difficult. There are three ways to
handle this case:
<OL>
<LI> Handle the not-present fault with a task. The task switch back to the
interrupted task will cause the processor to check the registers as it
loads them from the TSS.

<LI> 
<A HREF="PUSH.htm">PUSH</A> and 
<A HREF="POP.htm">POP</A> all segment registers. Each 
<A HREF="POP.htm">POP</A> causes the processor to
check the new contents of the segment register.

<LI> Scrutinize the contents of each segment-register image in the TSS,
simulating the test that the processor makes when it loads a segment
register.
</OL>
This exception pushes an error code onto the stack. The EXT bit of the
error code is set if an event external to the program caused an interrupt
that subsequently referenced a not-present segment. The I-bit is set if the
error code refers to an IDT entry, e.g., an 
<A HREF="INT.htm">INT</A> instruction referencing a
not-present gate.
<P>
An operating system typically uses the "segment not present" exception to
implement virtual memory at the segment level. A not-present indication in a
gate descriptor, however, usually does not indicate that a segment is not
present (because gates do not necessarily correspond to segments).
Not-present gates may be used by an operating system to trigger exceptions
of special significance to the operating system.

<H2>9.8.12 Interrupt 12 -- Stack Exception</H2>
A stack fault occurs in either of two general conditions:
<UL>
<LI> As a result of a limit violation in any operation that refers to the
SS register. This includes stack-oriented instructions such as 
<A HREF="POP.htm">POP</A>,
<A HREF="PUSH.htm">PUSH</A>, 
<A HREF="ENTER.htm">ENTER</A>, and 
<A HREF="LEAVE.htm">LEAVE</A>, as well as other memory references that
implicitly use SS (for example, <TT><A HREF="MOV.htm">MOV</A> AX, [BP+6]</TT>). 
<A HREF="ENTER.htm">ENTER</A> causes this
exception when the stack is too small for the indicated local-variable
space.
<LI> When attempting to load the SS register with a descriptor that is
marked not-present but is otherwise valid. This can occur in a task
switch, an interlevel 
<A HREF="CALL.htm">CALL</A>, an interlevel return, an 
<A HREF="LGS.htm">LSS</A> instruction,
or a <A HREF="MOV.htm">MOV</A> or <A HREF="POP.htm">POP</A> instruction to SS.
</UL>
When the processor detects a stack exception, it pushes an error code onto
the stack of the exception handler. If the exception is due to a not-present
stack segment or to overflow of the new stack during an interlevel 
<A HREF="CALL.htm">CALL</A>, the
error code contains a selector to the segment in question (the exception
handler can test the present bit in the descriptor to determine which
exception occurred); otherwise the error code is zero.
<P>
An instruction that causes this fault is restartable in all cases. The
return pointer pushed onto the exception handler's stack points to the
instruction that needs to be restarted. This instruction is usually the one
that caused the exception; however, in the case of a stack exception due to
loading of a not-present stack-segment descriptor during a task switch, the
indicated instruction is the first instruction of the new task.
<P>
When a stack fault occurs during a task switch, the segment registers may
not be usable for referencing memory. During a task switch, the selector
values are loaded before the descriptors are checked. If a stack fault is
discovered, the remaining segment registers have not been checked and
therefore may not be usable for referencing memory. The stack fault handler
should not rely on being able to use the values found in CS, SS, DS, ES,
FS, and GS without causing another exception. The exception handler should
check all segment registers before trying to resume the new task; otherwise,
general protection faults may result later under conditions that make
diagnosis more difficult.

<H2>9.8.13 Interrupt 13 -- General Protection Exception</H2>
All protection violations that do not cause another exception cause a
general protection exception. This includes (but is not limited to):
<OL>
<LI> Exceeding segment limit when using CS, DS, ES, FS, or GS
<LI> Exceeding segment limit when referencing a descriptor table
<LI> Transferring control to a segment that is not executable
<LI> Writing into a read-only data segment or into a code segment
<LI> Reading from an execute-only segment
<LI> Loading the SS register with a read-only descriptor (unless the
selector comes from the TSS during a task switch, in which case a TSS
exception occurs
<LI> Loading SS, DS, ES, FS, or GS with the descriptor of a system segment
<LI> Loading DS, ES, FS, or GS with the descriptor of an executable
segment that is not also readable
<LI> Loading SS with the descriptor of an executable segment
<LI> Accessing memory via DS, ES, FS, or GS when the segment register
contains a null selector
<LI> Switching to a busy task
<LI> Violating privilege rules
<LI> Loading CR0 with PG=1 and PE=0.
<LI> Interrupt or exception via trap or interrupt gate from V86 mode to
privilege level other than zero.
<LI> Exceeding the instruction length limit of 15 bytes (this can occur
only if redundant prefixes are placed before an instruction)
</OL>
The general protection exception is a fault. In response to a general
protection exception, the processor pushes an error code onto the exception
handler's stack. If loading a descriptor causes the exception, the error
code contains a selector to the descriptor; otherwise, the error code is
null. The source of the selector in an error code may be any of the
following:
<OL>
<LI> An operand of the instruction.
<LI> A selector from a gate that is the operand of the instruction.
<LI> A selector from a TSS involved in a task switch.
</OL>

<H2>9.8.14 Interrupt 14 -- Page Fault</H2>
This exception occurs when paging is enabled (PG=1) and the processor
detects one of the following conditions while translating a linear address
to a physical address:
<UL>
<LI> The page-directory or page-table entry needed for the address
translation has zero in its present bit.
<LI> The current procedure does not have sufficient privilege to access the
indicated page.
</UL>
The processor makes available to the page fault handler two items of
information that aid in diagnosing the exception and recovering from it:
<UL>
<LI> An error code on the stack. The error code for a page fault has a
format different from that for other exceptions (see 
<A HREF="#fig9-8">Figure 9-8</A>
  ). The
error code tells the exception handler three things:
<OL>
<LI> Whether the exception was due to a not present page or to an access
rights violation.
<LI> Whether the processor was executing at user or supervisor level at
the time of the exception.
<LI> Whether the memory access that caused the exception was a read or
write.
</OL>
<LI> CR2 (control register two). The processor stores in CR2 the linear
address used in the access that caused the exception (see 
<A HREF="#fig9-9">Figure 9-9</A>).
The exception handler can use this address to locate the corresponding
page directory and page table entries. If another page fault can occur
during execution of the page fault handler, the handler should push CR2
onto the stack.
</UL>
<P>
<A NAME="fig9-8">
<IMG align=center SRC="fig9-8.gif" border=0>
<P>

<H3>9.8.14.1  Page Fault During Task Switch</H3>
The processor may access any of four segments during a task switch:
<OL>
<LI> Writes the state of the original task in the TSS of that task.
<LI> Reads the GDT to locate the TSS descriptor of the new task.
<LI> Reads the TSS of the new task to check the types of segment
descriptors from the TSS.
<LI> May read the LDT of the new task in order to verify the segment
registers stored in the new TSS.
</OL>
A page fault can result from accessing any of these segments. In the latter
two cases the exception occurs in the context of the new task. The
instruction pointer refers to the next instruction of the new task, not to
the instruction that caused the task switch. If the design of the operating
system permits page faults to occur during task-switches, the page-fault
handler should be invoked via a task gate.
<P>
<A NAME="fig9-9">
<IMG align=center SRC="fig9-9.gif" border=0>

<H3>9.8.14.2  Page Fault with Inconsistent Stack Pointer</H3>
Special care should be taken to ensure that a page fault does not cause the
processor to use an invalid stack pointer (SS:ESP). Software written for
earlier processors in the 8086 family often uses a pair of instructions to
change to a new stack; for example:
<PRE>
<A HREF="MOV.htm">MOV</A> SS, AX
<A HREF="MOV.htm">MOV</A> SP, StackTop
</PRE>
With the 80386, because the second instruction accesses memory, it is
possible to get a page fault after SS has been changed but before SP has
received the corresponding change. At this point, the two parts of the stack
pointer SS:SP (or, for 32-bit programs, SS:ESP) are inconsistent.
<P>
The processor does not use the inconsistent stack pointer if the handling
of the page fault causes a stack switch to a well defined stack (i.e., the
handler is a task or a more privileged procedure). However, if the page
fault handler is invoked by a trap or interrupt gate and the page fault
occurs at the same privilege level as the page fault handler, the processor
will attempt to use the stack indicated by the current (invalid) stack
pointer.
<P>
In systems that implement paging and that handle page faults within the
faulting task (with trap or interrupt gates), software that executes at the
same privilege level as the page fault handler should initialize a new stack
by using the new 
<A HREF="LGS.htm">LSS</A> instruction rather than an instruction pair shown
above. When the page fault handler executes at privilege level zero (the
normal case), the scope of the problem is limited to privilege-level zero
code, typically the kernel of the operating system.

<H2>9.8.15 Interrupt 16 -- Coprocessor Error</H2>
The 80386 reports this exception when it detects a signal from the 80287 or
80387 on the 80386's ERROR# input pin. The 80386 tests this pin only at the
beginning of certain ESC instructions and when it encounters a 
<A HREF="WAIT.htm">WAIT</A>
instruction while the EM bit of the MSW is zero (no emulation). Refer to
<A HREF="c11.htm">Chapter 11</A>
   for more information on the coprocessor interface.
<P>
<HR>
<P>
<B>up:</B> <A HREF="c09.htm">
Chapter 9 -- Exceptions and Interrupts</A><BR>
<B>prev:</B> <A HREF="s09_07.htm">9.7  Error Code</A><BR>
<B>next:</B> <A HREF="s09_09.htm">9.9  Exception Summary</A>
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