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<!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN"><HTML><HEAD><TITLE>80386 Programmer's Reference Manual -- Section 9.8</TITLE></HEAD><BODY><B>up:</B> <A HREF="c09.htm">Chapter 9 -- Exceptions and Interrupts</A><BR><B>prev:</B> <A HREF="s09_07.htm">9.7 Error Code</A><BR><B>next:</B> <A HREF="s09_09.htm">9.9 Exception Summary</A><P><HR><P><H1>9.8 Exception Conditions</H1>The following sections describe each of the possible exception conditionsin detail. Each description classifies the exception as a fault, trap, orabort. This classification provides information needed by systemsprogrammers for restarting the procedure in which the exception occurred:<DL><DT>Faults <DD>The CS and EIP values saved when a fault is reported point to theinstruction causing the fault.<DT>Traps <DD>The CS and EIP values stored when the trap is reported point to theinstruction dynamically after the instruction causing the trap. Ifa trap is detected during an instruction that alters program flow,the reported values of CS and EIP reflect the alteration of programflow. For example, if a trap is detected in a <A HREF="JMP.htm">JMP</A> instruction, theCS and EIP values pushed onto the stack point to the target of the<A HREF="JMP.htm">JMP</A>, not to the instruction after the <A HREF="JMP.htm">JMP</A>.<DT>Aborts <DD>An abort is an exception that permits neither precise location ofthe instruction causing the exception nor restart of the programthat caused the exception. Aborts are used to report severe errors,such as hardware errors and inconsistent or illegal values insystem tables.</DL><H2>9.8.1 Interrupt 0 -- Divide Error</H2>The divide-error fault occurs during a <A HREF="DIV.htm">DIV</A> or an <A HREF="IDIV.htm">IDIV</A> instruction when thedivisor is zero.<H2>9.8.2 Interrupt 1 -- Debug Exceptions</H2>The processor triggers this interrupt for any of a number of conditions;whether the exception is a fault or a trap depends on the condition:<UL><LI> Instruction address breakpoint fault.<LI> Data address breakpoint trap.<LI> General detect fault.<LI> Single-step trap.<LI> Task-switch breakpoint trap.</UL>The processor does not push an error code for this exception. An exceptionhandler can examine the debug registers to determine which condition causedthe exception . Refer to <A HREF="c12.htm">Chapter 12</A> for more detailed information aboutdebugging and the debug registers.<H2>9.8.3 Interrupt 3 -- Breakpoint</H2>The <A HREF="INT.htm">INT</A> 3 instruction causes this trap. The <A HREF="INT.htm">INT</A> 3 instruction is one bytelong, which makes it easy to replace an opcode in an executable segment withthe breakpoint opcode. The operating system or a debugging subsystem can usea data-segment alias for an executable segment to place an <A HREF="INT.htm">INT</A> 3 anywhere itis convenient to arrest normal execution so that some sort of specialprocessing can be performed. Debuggers typically use breakpoints as a way ofdisplaying registers, variables, etc., at crucial points in a task.<P>The saved CS:EIP value points to the byte following the breakpoint. If adebugger replaces a planted breakpoint with a valid opcode, it must subtractone from the saved EIP value before returning . Refer also to <A HREF="c12.htm">Chapter 12</A> formore information on debugging.<H2>9.8.4 Interrupt 4 -- Overflow</H2>This trap occurs when the processor encounters an <A HREF="INT.htm">INTO</A> instruction and theOF (overflow) flag is set. Since signed arithmetic and unsigned arithmeticboth use the same arithmetic instructions, the processor cannot determinewhich is intended and therefore does not cause overflow exceptionsautomatically. Instead it merely sets OF when the results, if interpreted assigned numbers, would be out of range. When doing arithmetic on signedoperands, careful programmers and compilers either test OF directly or usethe <A HREF="INT.htm">INTO</A> instruction.<H2>9.8.5 Interrupt 5 -- Bounds Check</H2>This fault occurs when the processor, while executing a <A HREF="BOUND.htm">BOUND</A> instruction,finds that the operand exceeds the specified limits. A program can use the<A HREF="BOUND.htm">BOUND</A>instruction to check a signed array index against signed limitsdefined in a block of memory.<H2>9.8.6 Interrupt 6 -- Invalid Opcode</H2>This fault occurs when an invalid opcode is detected by the execution unit.(The exception is not detected until an attempt is made to execute theinvalid opcode; i.e., prefetching an invalid opcode does not cause thisexception.) No error code is pushed on the stack. The exception can behandled within the same task.<P>This exception also occurs when the type of operand is invalid for thegiven opcode. Examples include an intersegment <A HREF="JMP.htm">JMP</A> referencing a registeroperand, or an <A HREF="LGS.htm">LES</A> instruction with a register source operand.<H2>9.8.7 Interrupt 7 -- Coprocessor Not Available</H2>This exception occurs in either of two conditions:<UL><LI> The processor encounters an ESC (escape) instruction, and the EM(emulate) bit ofCR0 (control register zero) is set.<LI> The processor encounters either the <A HREF="WAIT.htm">WAIT</A> instruction or an ESCinstruction, and both the MP (monitor coprocessor) and TS (taskswitched) bits of CR0 are set.</UL>Refer to <A HREF="c11.htm">Chapter 11</A> for information about the coprocessor interface .<H2>9.8.8 Interrupt 8 -- Double Fault</H2>Normally, when the processor detects an exception while trying to invokethe handler for a prior exception, the two exceptions can be handledserially. If, however, the processor cannot handle them serially, it signalsthe double-fault exception instead. To determine when two faults are to besignalled as a double fault, the 80386 divides the exceptions into threeclasses: benign exceptions, contributory exceptions, and page faults. <A HREF="#Table 9-3">Table 9-3</A> shows this classification.<P><A HREF="#Table 9-4">Table 9-4</A> shows which combinations of exceptions cause a double fault andwhich do not.<P>The processor always pushes an error code onto the stack of thedouble-fault handler; however, the error code is always zero. The faultinginstruction may not be restarted. If any other exception occurs whileattempting to invoke the double-fault handler, the processor shuts down.<A NAME="Table 9-3"><PRE>Table 9-3. Double-Fault Detection ClassesClass ID Description 1 Debug exceptions 2 NMI 3 BreakpointBenign 4 OverflowExceptions 5 Bounds check 6 Invalid opcode 7 Coprocessor not available 16 Coprocessor error 0 Divide error 9 Coprocessor Segment OverrunContributory 10 Invalid TSSExceptions 11 Segment not present 12 Stack exception 13 General protectionPage Faults 14 Page fault</PRE></A><HR><A NAME="Table 9-4"><PRE>Table 9-4. Double-Fault DefinitionSECOND EXCEPTION Benign Contributory Page Exception Exception Fault Benign OK OK OK ExceptionFIRST Contributory OK DOUBLE OKEXCEPTION Exception Page Fault OK DOUBLE DOUBLE</PRE></A><H2>9.8.9 Interrupt 9 -- Coprocessor Segment Overrun</H2>This exception is raised in protected mode if the 80386 detects a page orsegment violation while transferring the middle portion of a coprocessoroperand to the NPX . This exception is avoidable. Refer to <A HREF="c11.htm">Chapter 11</A> formore information about the coprocessor interface.<H2>9.8.10 Interrupt 10 -- Invalid TSS</H2>Interrupt 10 occurs if during a task switch the new TSS is invalid. A TSSis considered invalid in the cases shown in <A HREF="#Table 9-5">Table 9-5</A>. An error code ispushed onto the stack to help identify the cause of the fault. The EXT bitindicates whether the exception was caused by a condition outside thecontrol of the program; e.g., an external interrupt via a task gatetriggered a switch to an invalid TSS.<P>This fault can occur either in the context of the original task or in thecontext of the new task. Until the processor has completely verified thepresence of the new TSS, the exception occurs in the context of the originaltask. Once the existence of the new TSS is verified, the task switch isconsidered complete; i.e., TR is updated and, if the switch is due to a<A HREF="CALL.htm">CALL</A> or interrupt, the backlink of the new TSS is set to the old TSS. Anyerrors discovered by the processor after this point are handled in thecontext of the new task.<P>To insure a proper TSS to process it, the handler for exception 10 must bea task invoked via a task gate.<A NAME="Table 9-5"><PRE>Table 9-5. Conditions That Invalidate the TSSError Code ConditionTSS id + EXT The limit in the TSS descriptor is less than 103LTD id + EXT Invalid LDT selector or LDT not presentSS id + EXT Stack segment selector is outside table limitSS id + EXT Stack segment is not a writable segmentSS id + EXT Stack segment DPL does not match new CPLSS id + EXT Stack segment selector RPL < > CPLCS id + EXT Code segment selector is outside table limitCS id + EXT Code segment selector does not refer to code segmentCS id + EXT DPL of non-conforming code segment < > new CPLCS id + EXT DPL of conforming code segment > new CPLDS/ES/FS/GS id + EXT DS, ES, FS, or GS segment selector is outside table limitsDS/ES/FS/GS id + EXT DS, ES, FS, or GS is not readable segment</PRE>⌨️ 快捷键说明
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