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<!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN"><HTML><HEAD><TITLE>80386 Programmer's Reference Manual -- Opcode LGDT</TITLE></HEAD><BODY><B>up:</B> <A HREF="c17.htm">Chapter 17 -- 80386 Instruction Set</A><BR><B>prev:</B><A HREF="LEAVE.htm"> LEAVE High Level Procedure Exit</A><BR><B>next:</B><A HREF="LGS.htm"> LGS/LSS/LDS/LES/LFS Load Full Pointer</A><P><HR><P><H1>LGDT/LIDT -- Load Global/Interrupt Descriptor Table Register</H1><PRE>Opcode Instruction Clocks Description0F 01 /2 LGDT m16&32 11 Load m into GDTR0F 01 /3 LIDT m16&32 11 Load m into IDTR</PRE><H2>Operation</H2><PRE>IF instruction = LIDTTHEN IF OperandSize = 16 THEN IDTR.Limit:Base := m16:24 (* 24 bits of base loaded *) ELSE IDTR.Limit:Base := m16:32 FI;ELSE (* instruction = LGDT *) IF OperandSize = 16 THEN GDTR.Limit:Base := m16:24 (* 24 bits of base loaded *) ELSE GDTR.Limit:Base := m16:32; FI;FI;</PRE><H2>Description</H2>The LGDT and LIDT instructions load a linear base address and limitvalue from a six-byte data operand in memory into the GDTR or IDTR,respectively. If a 16-bit operand is used with LGDT or LIDT, theregister is loaded with a 16-bit limit and a 24-bit base, and thehigh-order eight bits of the six-byte data operand are not used. If a 32-bitoperand is used, a 16-bit limit and a 32-bit base is loaded; the high-ordereight bits of the six-byte operand are used as high-order base address bits.<P>The <A HREF="SGDT.htm">SGDT</A> and <A HREF="SGDT.htm">SIDT</A> instructions always store into all 48 bits of thesix-byte data operand. With the 80286, the upper eight bits are undefinedafter <A HREF="SGDT.htm">SGDT</A> or <A HREF="SGDT.htm">SIDT</A> is executed. With the 80386, the upper eight bitsare written with the high-order eight address bits, for both a 16-bitoperand and a 32-bit operand. If LGDT or LIDT is used with a 16-bitoperand to load the register stored by SGDT or SIDT, the upper eightbits are stored as zeros.<P>LGDT and LIDT appear in operating system software; they are not usedin application programs. They are the only instructions that directly loada linear address (i.e., not a segment relative address) in 80386 ProtectedMode.<H2>Flags Affected</H2>None<H2>Protected Mode Exceptions</H2>#GP(0) if the current privilege level is not 0; #UD if the source operandis a register; #GP(0) for an illegal memory operand effective address inthe CS, DS, ES, FS, or GS segments; #SS(0) for an illegal address inthe SS segment; #PF(fault-code) for a page fault<H2>Real Address Mode Exceptions</H2>Interrupt 13 if any part of the operand would lie outside of the effectiveaddress space from 0 to 0FFFFH; Interrupt 6 if the source operand is aregister<EM><H3>Note</H3> These instructions are valid in Real Address Mode to allow power-up initialization for Protected Mode</EM><H2>Virtual 8086 Mode Exceptions</H2>Same exceptions as in Real Address Mode; #PF(fault-code) for a pagefault<P><HR><P><B>up:</B> <A HREF="c17.htm">Chapter 17 -- 80386 Instruction Set</A><BR><B>prev:</B><A HREF="LEAVE.htm"> LEAVE High Level Procedure Exit</A><BR><B>next:</B><A HREF="LGS.htm"> LGS/LSS/LDS/LES/LFS Load Full Pointer</A></BODY>⌨️ 快捷键说明
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