📄 s15_01.htm
字号:
<!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN"><HTML><HEAD><TITLE>80386 Programmer's Reference Manual -- Section 15.1</TITLE></HEAD><BODY><B>up:</B> <A HREF="c15.htm">Chapter 15 -- Virtual 8086 Mode</A><BR><B>prev:</B> <A HREF="c15.htm">Chapter 15 -- Virtual 8086 Mode</A><BR><B>next:</B> <A HREF="s15_02.htm">15.2 Structure of a V86 Task</A><P><HR><P><H1>15.1 Executing 8086 Code</H1>The processor executes in V86 mode when the VM (virtual machine) bit in theEFLAGS register is set. The processor tests this flag under two generalconditions:<OL><LI> When loading segment registers to know whether to use 8086-styleaddress formation.<LI> When decoding instructions to determine which instructions aresensitive to IOPL.</OL>Except for these two modifications to its normal operations, the 80386 inV86 mode operated much as in protected mode.<H2>15.1.1 Registers and Instructions</H2>The register set available in V86 mode includes all the registers definedfor the 8086 plus the new registers introduced by the 80386: FS, GS, debugregisters, control registers, and test registers. New instructions thatexplicitly operate on the segment registers FS and GS are available, and thenew segment-override prefixes can be used to cause instructions to utilizeFS and GS for address calculations. Instructions can utilize 32-bitoperands through the use of the operand size prefix.<P>8086 programs running as V86 tasks are able to take advantage of the newapplications-oriented instructions added to the architecture by theintroduction of the 80186/80188, 80286 and 80386:<UL><LI> New instructions introduced by 80186/80188 and 80286.<UL><LI> <A HREF="PUSH.htm">PUSH</A> immediate data<LI> Push all and pop all (<A HREF="PUSHA.htm">PUSHA</A> and <A HREF="POPA.htm">POPA</A>)<LI> Multiply immediate data<LI> Shift and rotate by immediate count<LI> String I/O<LI> <A HREF="ENTER.htm">ENTER</A> and <A HREF="LEAVE.htm">LEAVE</A><LI> <A HREF="BOUND.htm">BOUND</A></UL><LI> New instructions introduced by 80386.<UL><LI> <A HREF="LGS.htm">LSS</A>, <A HREF="LGS.htm">LFS</A>, <A HREF="LGS.htm">LGS</A> instructions<LI> Long-displacement conditional jumps<LI> Single-bit instructions<LI> Bit scan<LI> Double-shift instructions<LI> Byte set on condition<LI> Move with sign/zero extension<LI> Generalized multiply</UL></UL><H2>15.1.2 Linear Address Formation</H2>In V86 mode, the 80386 processor does not interpret 8086 selectors byreferring to descriptors; instead, it forms linear addresses as an 8086would. It shifts the selector left by four bits to form a 20-bit baseaddress. The effective address is extended with four high-order zeros andadded to the base address to create a linear address as <A HREF="#fig15-1">Figure 15-1</A>illustrates.<P>Because of the possibility of a carry, the resulting linear address maycontain up to 21 significant bits. An 8086 program may generate linearaddresses anywhere in the range 0 to 10FFEFH (one megabyte plusapproximately 64 Kbytes) of the task's linear address space.<P>V86 tasks generate 32-bit linear addresses. While an 8086 program can onlyutilize the low-order 21 bits of a linear address, the linear address can bemapped via page tables to any 32-bit physical address.<P>Unlike the 8086 and 80286, 32-bit effective addresses can be generated (viathe address-size prefix); however, the value of a 32-bit address may notexceed 65,535 without causing an exception. For full compatibility with80286 real-address mode, pseudo-protection faults (interrupt 12 or 13 withno error code) occur if an address is generated outside the range 0 through65,535.<P><A NAME="fig15-1"><IMG align=center SRC="fig15-1.gif" border=0><P><HR><P><B>up:</B> <A HREF="c15.htm">Chapter 15 -- Virtual 8086 Mode</A><BR><B>prev:</B> <A HREF="c15.htm">Chapter 15 -- Virtual 8086 Mode</A><BR><B>next:</B> <A HREF="s15_02.htm">15.2 Structure of a V86 Task</A></BODY>⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -