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<!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN"><HTML><HEAD><TITLE>80386 Programmer's Reference Manual -- Section 7.5</TITLE></HEAD><BODY><B>up:</B> <A HREF="c07.htm">Chapter 7 -- Multitasking</A><BR><B>prev:</B> <A HREF="s07_04.htm">7.4 Task Gate Descriptor</A><BR><B>next:</B> <A HREF="s07_06.htm">7.6 Task Linking</A><P><HR><P><H1>7.5 Task Switching</H1>The 80386 switches execution to another task in any of four cases:<OL><LI> The current task executes a <A HREF="JMP.htm">JMP</A> or <A HREF="CALL.htm">CALL</A> that refers to a TSSdescriptor.<LI> The current task executes a <A HREF="JMP.htm">JMP</A> or <A HREF="CALL.htm">CALL</A> that refers to a task gate.<LI> An interrupt or exception vectors to a task gate in the IDT.<LI> The current task executes an <A HREF="IRET.htm">IRET</A> when the NT flag is set.</OL><A HREF="JMP.htm">JMP</A>, <A HREF="CALL.htm">CALL</A>, <A HREF="IRET.htm">IRET</A>, interrupts, and exceptions are all ordinary mechanisms ofthe 80386 that can be used in circumstances that do not require a taskswitch. Either the type of descriptor referenced or the NT (nested task) bitin the flag word distinguishes between the standard mechanism and thevariant that causes a task switch.<P>To cause a task switch, a <A HREF="JMP.htm">JMP</A> or <A HREF="CALL.htm">CALL</A> instruction can refer either to a TSSdescriptor or to a task gate. The effect is the same in either case: the80386 switches to the indicated task.<P>An exception or interrupt causes a task switch when it vectors to a taskgate in the IDT. If it vectors to an interrupt or trap gate in the IDT, atask switch does not occur . Refer to <A HREF="c09.htm">Chapter 9</A> for more information on theinterrupt mechanism.<P>Whether invoked as a task or as a procedure of the interrupted task, aninterrupt handler always returns control to the interrupted procedure in theinterrupted task. If the NT flag is set, however, the handler is aninterrupt task, and the <A HREF="IRET.htm">IRET</A> switches back to the interrupted task.<P>A task switching operation involves these steps:<OL><LI> Checking that the current task is allowed to switch to the designatedtask. Data-access privilege rules apply in the case of <A HREF="JMP.htm">JMP</A> or <A HREF="CALL.htm">CALL</A>instructions. The DPL of the TSS descriptor or task gate must be numerically greater (e.g., lower privilege level)than or equal to the maximum of CPL and the RPL of the gate selector.Exceptions, interrupts, and <A HREF="IRET.htm">IRET</A> are permitted to switch tasksregardless of the DPL of the target task gate or TSS descriptor.<LI> Checking that the TSS descriptor of the new task is marked presentand has a valid limit. Any errors up to this point occur in thecontext of the outgoing task. Errors are restartable and can behandled in a way that is transparent to applications procedures.<LI> Saving the state of the current task. The processor finds the baseaddress of the current TSS cached in the task register. It copies theregisters into the current TSS (EAX, ECX, EDX, EBX, ESP, EBP, ESI,EDI, ES, CS, SS, DS, FS, GS, and the flag register). The EIP field ofthe TSS points to the instruction after the one that caused the taskswitch.<LI> Loading the task register with the selector of the incoming task'sTSS descriptor, marking the incoming task's TSS descriptor as busy,and setting the TS (task switched) bit of the MSW. The selector iseither the operand of a control transfer instruction or is taken froma task gate.<LI> Loading the incoming task's state from its TSS and resumingexecution. The registers loaded are the LDT register; the flagregister; the general registers EIP, EAX, ECX, EDX, EBX, ESP, EBP,ESI, EDI; the segment registers ES, CS, SS, DS, FS, and GS; and PDBR.Any errors detected in this step occur in the context of the incomingtask. To an exception handler, it appears that the first instructionof the new task has not yet executed.</OL>Note that the state of the outgoing task is always saved when a task switchoccurs. If execution of that task is resumed, it starts after theinstruction that caused the task switch. The registers are restored to thevalues they held when the task stopped executing.<P>Every task switch sets the TS (task switched) bit in the MSW (machinestatus word). The TS flag is useful to systems software when a coprocessor(such as a numerics coprocessor) is present. The TS bit signals that thecontext of the coprocessor may not correspond to the current 80386 task.<A HREF="c11.htm">Chapter 11</A> discusses the TS bit and coprocessors in more detail .<P>Exception handlers that field task-switch exceptions in the incoming task(exceptions due to tests 4 thru 16 of Table 7-1) should be cautious abouttaking any action that might load the selector that caused the exception.Such an action will probably cause another exception, unless the exceptionhandler first examines the selector and fixes any potential problem.<P>The privilege level at which execution resumes in the incoming task isneither restricted nor affected by the privilege level at which the outgoingtask was executing. Because the tasks are isolated by their separate addressspaces and TSSs and because privilege rules can be used to prevent improperaccess to a TSS, no privilege rules are needed to constrain the relationbetween the CPLs of the tasks. The new task begins executing at theprivilege level indicated by the RPL of the CS selector value that is loadedfrom the TSS.<PRE>Table 7-1. Checks Made during a Task SwitchNP = Segment-not-present exception GP = General protection fault TS = Invalid TSS SF = Stack faultValidity tests of a selector check that the selector is in the propertable (e.g., the LDT selector refers to the GDT), lies within the bounds ofthe table, and refers to the proper type of descriptor (e.g., the LDTselector refers to an LDT descriptor).Test Test Description Exception Error Code Selects 1 Incoming TSS descriptor is present NP Incoming TSS 2 Incoming TSS descriptor is marked not-busy GP Incoming TSS marked not-busy 3 Limit of incoming TSS is greater than or equal to 103 TS Incoming TSS -- All register and selector values are loaded -- 4 LDT selector of incoming task is valid TS Incoming TSS 5 LDT of incoming task is present TS Incoming TSS 6 CS selector is valid TS Code segment 7 Code segment is present NP Code segment 8 Code segment DPL matches CS RPL TS Code segment 9 Stack segment is valid GP Stack segment 10 Stack segment is present SF Stack segment 11 Stack segment DPL = CPL SF Stack segment 12 Stack-selector RPL = CPL GP Stack segment 13 DS, ES, FS, GS selectors are valid GP Segment 14 DS, ES, FS, GS segments are readable GP Segment 15 DS, ES, FS, GS segments are present NP Segment 16 DS, ES, FS, GS segment DPL >= CPL (unless these are conforming segments) GP Segment</PRE><P><HR><P><B>up:</B> <A HREF="c07.htm">Chapter 7 -- Multitasking</A><BR><B>prev:</B> <A HREF="s07_04.htm">7.4 Task Gate Descriptor</A><BR><B>next:</B> <A HREF="s07_06.htm">7.6 Task Linking</A></BODY>⌨️ 快捷键说明
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