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<!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN"><HTML><HEAD><TITLE>80386 Programmer's Reference Manual -- Section 5.2</TITLE></HEAD><BODY><B>up:</B> <A HREF="c05.htm">Chapter 5 -- Memory Management</A><BR><B>prev:</B> <A HREF="s05_01.htm">5.1 Segment Translation</A><BR><B>next:</B> <A HREF="s05_03.htm">5.3 Combining Segment and Page Translation</A><P><HR><P><H1>5.2 Page Translation</H1>In the second phase of address transformation, the 80386 transforms alinear address into a physical address. This phase of address transformationimplements the basic features needed for page-oriented virtual-memorysystems and page-level protection.<P>The page-translation step is optional. Page translation is in effect onlywhen the PG bit of CR0 is set. This bit is typically set by the operatingsystem during software initialization. The PG bit must be set if theoperating system is to implement multiple virtual 8086 tasks, page-orientedprotection, or page-oriented virtual memory.<H2>5.2.1 Page Frame</H2>A page frame is a 4K-byte unit of contiguous addresses of physical memory.Pages begin onbyte boundaries and are fixed in size.<H2>5.2.2 Linear Address</H2>A linear address refers indirectly to a physical address by specifying apage table, a page within that table, and an offset within that page. <A HREF="#fig5-8">Figure 5-8</A> shows the format of a linear address.<P><A HREF="#fig5-9">Figure 5-9</A> shows how the processor converts the DIR, PAGE, and OFFSETfields of a linear address into the physical address by consulting twolevels of page tables. The addressing mechanism uses the DIR field as anindex into a page directory, uses the PAGE field as an index into the pagetable determined by the page directory, and uses the OFFSET field to addressa byte within the page determined by the page table.<P><A NAME="fig5-8"><IMG align=center SRC="fig5-8.gif" border=0><P><HR><P><A NAME="fig5-9"><IMG align=center SRC="fig5-9.gif" border=0><P><H2>5.2.3 Page Tables</H2>A page table is simply an array of 32-bit page specifiers. A page table isitself a page, and therefore contains 4 Kilobytes of memory or at most 1K32-bit entries.<P>Two levels of tables are used to address a page of memory. At the higherlevel is a page directory. The page directory addresses up to 1K page tablesof the second level. A page table of the second level addresses up to 1Kpages. All the tables addressed by one page directory, therefore, canaddress 1M pages (2^(20)). Because each page contains 4K bytes 2^(12)bytes), the tables of one page directory can span the entire physicaladdress space of the 80386 (2^(20) times 2^(12) = 2^(32)).<P>The physical address of the current page directory is stored in the CPUregister CR3, also called the page directory base register (PDBR). Memorymanagement software has the option of using one page directory for alltasks, one page directory for each task, or some combination of the two.Refer to <A HREF="c10.htm">Chapter 10</A> for information on initialization of CR3 . Refer to<A HREF="c07.htm">Chapter 7</A> to see how CR3 can change for each task .<H2>5.2.4 Page-Table Entries</H2>Entries in either level of page tables have the same format. <A HREF="#fig5-10">Figure 5-10</A> illustrates this format.<H3>5.2.4.1 Page Frame Address</H3>The page frame address specifies the physical starting address of a page.Because pages are located on 4K boundaries, the low-order 12 bits are alwayszero. In a page directory, the page frame address is the address of a pagetable. In a second-level page table, the page frame address is the addressof the page frame that contains the desired memory operand.<H3>5.2.4.2 Present Bit</H3>The Present bit indicates whether a page table entry can be used in addresstranslation. P=1 indicates that the entry can be used.<P>When P=0 in either level of page tables, the entry is not valid for addresstranslation, and the rest of the entry is available for software use; noneof the other bits in the entry is tested by the hardware. <A HREF="#fig5-11">Figure 5-11</A> illustrates the format of a page-table entry when P=0.<P>If P=0 in either level of page tables when an attempt is made to use apage-table entry for address translation, the processor signals a pageexception. In software systems that support paged virtual memory, thepage-not-present exception handler can bring the required page into physicalmemory. The instruction that caused the exception can then be reexecuted.Refer to <A HREF="c09.htm">Chapter 9</A> for more information on exception handlers .<P>Note that there is no present bit for the page directory itself. The pagedirectory may be not-present while the associated task is suspended, but theoperating system must ensure that the page directory indicated by the CR3image in the TSS is present in physical memory before the task isdispatched . Refer to <A HREF="c07.htm">Chapter 7</A> for an explanation of the TSS and taskdispatching.<P><A NAME="fig5-10"><IMG align=center SRC="fig5-10.gif" border=0><P><HR><P><A NAME="fig5-11"><IMG align=center SRC="fig5-11.gif" border=0><P><H3>5.2.4.3 Accessed and Dirty Bits</H3>These bits provide data about page usage in both levels of the page tables.With the exception of the dirty bit in a page directory entry, these bitsare set by the hardware; however, the processor does not clear any of thesebits.<P>The processor sets the corresponding accessed bits in both levels of pagetables to one before a read or write operation to a page.<P>The processor sets the dirty bit in the second-level page table to onebefore a write to an address covered by that page table entry. The dirty bitin directory entries is undefined.<P>An operating system that supports paged virtual memory can use these bitsto determine what pages to eliminate from physical memory when the demandfor memory exceeds the physical memory available. The operating system isresponsible for testing and clearing these bits.<P>Refer to <A HREF="c11.htm">Chapter 11</A> for how the 80386 coordinates updates to the accessedand dirty bits in multiprocessor systems.<H3>5.2.4.4 Read/Write and User/Supervisor Bits</H3>These bits are not used for address translation, but are used forpage-level protection, which the processor performs at the same time asaddress translation . Refer to <A HREF="c06.htm">Chapter 6</A> where protection is discussed indetail.<H2>5.2.5 Page Translation Cache</H2>For greatest efficiency in address translation, the processor stores themost recently used page-table data in an on-chip cache. Only if thenecessary paging information is not in the cache must both levels of pagetables be referenced.<P>The existence of the page-translation cache is invisible to applicationsprogrammers but not to systems programmers; operating-system programmersmust flush the cache whenever the page tables are changed. Thepage-translation cache can be flushed by either of two methods:<OL><LI> By reloading CR3 with a <A HREF="MOVRS.htm">MOV</A> instruction; for example:<PRE><A HREF="MOVRS.htm">MOV</A> CR3, EAX</PRE><LI> By performing a task switch to a TSS that has a different CR3 imagethan the current TSS . (Refer to <A HREF="c07.htm">Chapter 7</A> for more information ontask switching.)</OL><P><HR><P><B>up:</B> <A HREF="c05.htm">Chapter 5 -- Memory Management</A><BR><B>prev:</B> <A HREF="s05_01.htm">5.1 Segment Translation</A><BR><B>next:</B> <A HREF="s05_03.htm">5.3 Combining Segment and Page Translation</A></BODY>⌨️ 快捷键说明
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