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<!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN"><HTML><HEAD><TITLE>80386 Programmer's Reference Manual -- Section 9.4</TITLE></HEAD><BODY><B>up:</B> <A HREF="c09.htm">Chapter 9 -- Exceptions and Interrupts</A><BR><B>prev:</B> <A HREF="s09_03.htm">9.3 Priority Among Simultaneous Interrupts and Exceptions</A><BR><B>next:</B> <A HREF="s09_05.htm">9.5 IDT Descriptors</A><P><HR><P><H1>9.4 Interrupt Descriptor Table</H1>The interrupt descriptor table (IDT) associates each interrupt or exceptionidentifier with a descriptor for the instructions that service theassociated event. Like the GDT and LDTs, the IDT is an array of 8-bytedescriptors. Unlike the GDT and LDTs, the first entry of the IDT may containa descriptor. To form an index into the IDT, the processor multiplies theinterrupt or exception identifier by eight. Because there are only 256identifiers, the IDT need not contain more than 256 descriptors. It cancontain fewer than 256 entries; entries are required only for interruptidentifiers that are actually used.<P>The IDT may reside anywhere in physical memory. As <A HREF="#fig9-1">Figure 9-1</A> shows, theprocessor locates the IDT by means of the IDT register (IDTR). Theinstructions <A HREF="LGDT.htm">LIDT</A> and <A HREF="SGDT.htm">SIDT</A> operate on the IDTR. Both instructions have oneexplicit operand: the address in memory of a 6-byte area. <A HREF="#fig9-2">Figure 9-2</A> showsthe format of this area.<P><A HREF="LGDT.htm">LIDT</A> (Load IDT register) loads the IDT register with the linear baseaddress and limit values contained in the memory operand. This instructioncan be executed only when the CPL is zero. It is normally used by theinitialization logic of an operating system when creating an IDT. Anoperating system may also use it to change from one IDT to another.<P><A HREF="SGDT.htm">SIDT</A> (Store IDT register) copies the base and limit value stored in IDTRto a memory location. This instruction can be executed at any privilegelevel.<A NAME="Table 9-2"><PRE>Table 9-2. Priority Among Simultaneous Interrupts and ExceptionsPriority Class of Interrupt or ExceptionHIGHEST Faults except debug faultsTrap instructions INTO, INT n, INT 3Debug traps for this instructionDebug faults for next instructionNMI interruptLOWEST INTR interrupt</PRE></A><A NAME="fig9-1"><IMG align=center SRC="fig9-1.gif" border=0><P><A NAME="fig9-2"><IMG align=center SRC="fig9-2.gif" border=0><P><HR><P><B>up:</B> <A HREF="c09.htm">Chapter 9 -- Exceptions and Interrupts</A><BR><B>prev:</B> <A HREF="s09_03.htm">9.3 Priority Among Simultaneous Interrupts and Exceptions</A><BR><B>next:</B> <A HREF="s09_05.htm">9.5 IDT Descriptors</A></BODY>⌨️ 快捷键说明
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