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<!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN"><HTML><HEAD><TITLE>80386 Programmer's Reference Manual -- Section 4.1</TITLE></HEAD><BODY><B>up:</B> <A HREF="c04.htm">Chapter 4 -- Systems Architecture</A><BR><B>prev:</B> <A HREF="c04.htm">Chapter 4 -- Systems Architecture</A><BR><B>next:</B> <A HREF="s04_02.htm">4.2 Systems Instructions</A><P><HR><P><H1>4.1 Systems Registers</H1>The registers designed for use by systems programmers fall into theseclasses:<UL><LI>EFLAGS<LI>Memory-Management Registers<LI>Control Registers<LI>Debug Registers<LI>Test Registers</UL><H2>4.1.1 Systems Flags</H2>The systems flags of the EFLAGS register control I/O, maskable interrupts,debugging, task switching, and enabling of virtual 8086 execution in aprotected, multitasking environment. These flags are highlighted in <A HREF="#fig4-1">Figure 4-1</A> .<DL><DT>IF (Interrupt-Enable Flag, bit 9)<DD>Setting IF allows the CPU to recognize external (maskable) interruptrequests. Clearing IF disables these interrupts. IF has no effect oneither exceptions or nonmaskable external interrupts . Refer to <A HREF="c09.htm">Chapter 9</A> for more details about interrupts .<DT>NT (Nested Task, bit 14)<DD>The processor uses the nested task flag to control chaining ofinterrupted and called tasks. NT influences the operation of the <A HREF="IRET.htm">IRET</A>instruction . Refer to <A HREF="c07.htm">Chapter 7</A> and <A HREF="c09.htm">Chapter 9</A>for more information onnested tasks.<DT>RF (Resume Flag, bit 16)<DD>The RF flag temporarily disables debug exceptions so that an instructioncan be restarted after a debug exception without immediately causinganother debug exception . Refer to <A HREF="c12.htm">Chapter 12</A> for details .<DT>TF (Trap Flag, bit 8)<DD>Setting TF puts the processor into single-step mode for debugging. Inthis mode, the CPU automatically generates an exception after eachinstruction, allowing a program to be inspected as it executes eachinstruction. Single-stepping is just one of several debugging features ofthe 80386 . Refer to <A HREF="c12.htm">Chapter 12</A> for additional information .<DT>VM (Virtual 8086 Mode, bit 17)<DD>When set, the VM flag indicates that the task is executing an 8086program . Refer to <A HREF="c14.htm">Chapter 14</A> for a detailed discussion of how the 80386executes 8086 tasks in a protected, multitasking environment.</DL><A NAME="fig4-1"><IMG align=center SRC="fig4-1.gif" border=0><H2>4.1.2 Memory-Management Registers</H2>Four registers of the 80386 locate the data structures that controlsegmented memory management:<DL><DT>GDTR Global Descriptor Table Register<DT>LDTR Local Descriptor Table Register<DD>These registers point to the segment descriptor tables GDT and LDT.Refer to <A HREF="c05.htm">Chapter 5</A> for an explanation of addressing via descriptortables.<DT>IDTR Interrupt Descriptor Table Register<DD>This register points to a table of entry points for interrupt handlers(the IDT ) . Refer to <A HREF="c09.htm">Chapter 9</A> for details of the interrupt mechanism .<DT>TR Task Register<DD>This register points to the information needed by the processor to definethe current task . Refer to <A HREF="c07.htm">Chapter 7</A> for a description of themultitasking features of the 80386.</DL><H2>4.1.3 Control Registers</H2><A HREF="#fig4-2">Figure 4-2</A> shows the format of the 80386 control registers CR0, CR2, andCR3. These registers are accessible to systems programmers only via variantsof the <A HREF="MOV.htm">MOV</A> instruction, which allow them to be loaded from or stored ingeneral registers; for example:<PRE>MOV EAX, CR0MOV CR3, EBX</PRE>CR0 contains system control flags, which control or indicate conditionsthat apply to the system as a whole, not to an individual task.<DL><DT>EM (Emulation, bit 2)<DD>EM indicates whether coprocessor functions are to be emulated. Refer to<A HREF="c11.htm">Chapter 11</A> for details .<DT>ET (Extension Type, bit 4)<DD>ET indicates the type of coprocessor present in the system (80287 or80387 ) . Refer to <A HREF="c11.htm">Chapter 11</A> and <A HREF="c10.htm">Chapter 10</A> for details.<DT>MP (Math Present, bit 1)<DD>MP controls the function of the <A HREF="WAIT.htm">WAIT</A> instruction, which is used tocoordinate a coprocessor . Refer to <A HREF="c11.htm">Chapter 11</A> for details .<DT>PE (Protection Enable, bit 0)<DD>Setting PE causes the processor to begin executing in protected mode.Resetting PE returns to real-address mode . Refer to <A HREF="c14.htm">Chapter 14</A> and<A HREF="c10.htm">Chapter 10</A> for more information on changing processor modes .<DT>PG (Paging, bit 31)<DD>PG indicates whether the processor uses page tables to translate linearaddresses into physical addresses . Refer to <A HREF="c05.htm">Chapter 5</A> for a descriptionof page translation; refer to <A HREF="c10.htm">Chapter 10</A> for a discussion of how to setPG.<DT>TS (Task Switched, bit 3)<DD>The processor sets TS with every task switch and tests TS wheninterpreting coprocessor instructions . Refer to <A HREF="c11.htm">Chapter 11</A> for details .</DL>CR2 is used for handling page faults when PG is set. The processor storesin CR2 the linear address that triggers the fault . Refer to <A HREF="c09.htm">Chapter 9</A> for adescription of page-fault handling.<P>CR3 is used when PG is set. CR3 enables the processor to locate the pagetable directory for the current task . Refer to <A HREF="c05.htm">Chapter 5</A> for a descriptionof page tables and page translation.<P><A NAME="fig4-2"><IMG align=center SRC="fig4-2.gif" border=0><P><H2>4.1.4 Debug Register</H2>The debug registers bring advanced debugging abilities to the 80386,including data breakpoints and the ability to set instruction breakpointswithout modifying code segments . Refer to <A HREF="c12.htm">Chapter 12</A> for a completedescription of formats and usage.<H2>4.1.5 Test Registers</H2>The test registers are not a standard part of the 80386 architecture. Theyare provided solely to enable confidence testing of the translationlookaside buffer (TLB), the cache used for storing information from pagetables . <A HREF="c12.htm">Chapter 12</A> explains how to use these registers .<P><HR><P><B>up:</B> <A HREF="c04.htm">Chapter 4 -- Systems Architecture</A><BR><B>prev:</B> <A HREF="c04.htm">Chapter 4 -- Systems Architecture</A><BR><B>next:</B> <A HREF="s04_02.htm">4.2 Systems Instructions</A></BODY>⌨️ 快捷键说明
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