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📁 Programmer s Reference Manual is an improtant book on Intel processor architecture and programming.
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<!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN"><HTML><HEAD><TITLE>80386 Programmer's Reference Manual -- Section 2.2</TITLE></HEAD><BODY><B>up:</B> <A HREF="c02.htm">Chapter 2 -- Basic Programming Model</A><BR><B>prev:</B> <A HREF="s02_01.htm">2.1  Memory Organization and Segmentation</A><BR><B>next:</B> <A HREF="s02_03.htm">2.3  Registers</A><P><HR><P><H1>2.2  Data Types</H1>Bytes, words, and doublewords are the fundamental data types (refer to<A HREF="#fig2-2">Figure 2-2</A>  ). A byte is eight contiguous bits starting at any logicaladdress. The bits are numbered 0 through 7; bit zero is the leastsignificant bit.<P>A word is two contiguous bytes starting at any byte address. A word thuscontains 16 bits. The bits of a word are numbered from 0 through 15; bit 0is the least significant bit. The byte containing bit 0 of the word iscalled the low byte; the byte containing bit 15 is called the high byte.<P>Each byte within a word has its own address, and the smaller of theaddresses is the address of the word. The byte at this lower addresscontains the eight least significant bits of the word, while the byte at thehigher address contains the eight most significant bits.<P>A doubleword is two contiguous words starting at any byte address. Adoubleword thus contains 32 bits. The bits of a doubleword are numbered from0 through 31; bit 0 is the least significant bit. The word containing bit 0of the doubleword is called the low word; the word containing bit 31 iscalled the high word.<P>Each byte within a doubleword has its own address, and the smallest of theaddresses is the address of the doubleword. The byte at this lowest addresscontains the eight least significant bits of the doubleword, while the byteat the highest address contains the eight most significant bits. <A HREF="#fig2-3">Figure 2-3</A> illustrates the arrangement of bytes within words anddoublewords.<P>Note that words need not be aligned at even-numbered addresses anddoublewords need not be aligned at addresses evenly divisible by four. Thisallows maximum flexibility in data structures (e.g., records containingmixed byte, word, and doubleword items) and efficiency in memoryutilization. When used in a configuration with a 32-bit bus, actualtransfers of data between processor and memory take place in units ofdoublewords beginning at addresses evenly divisible by four; however, theprocessor converts requests for misaligned words or doublewords into theappropriate sequences of requests acceptable to the memory interface. Suchmisaligned data transfers reduce performance by requiring extra memorycycles. For maximum performance, data structures (including stacks) shouldbe designed in such a way that, whenever possible, word operands are alignedat even addresses and doubleword operands are aligned at addresses evenlydivisible by four. Due to instruction prefetching and queuing within theCPU, there is no requirement for instructions to be aligned on word ordoubleword boundaries. (However, a slight increase in speed results if thetarget addresses of control transfers are evenly divisible by four.)<P>Although bytes, words, and doublewords are the fundamental types ofoperands, the processor also supports additional interpretations of theseoperands. Depending on the instruction referring to the operand, thefollowing additional data types are recognized:<DL><DT>Integer:<DD>A signed binary numeric value contained in a 32-bit doubleword, 16-bit word,or 8-bit byte. All operations assume a 2's complement representation. Thesign bit is located in bit 7 in a byte, bit 15 in a word, and bit 31 in adoubleword. The sign bit has the value zero for positive integers and onefor negative. Since the high-order bit is used for a sign, the range of an8-bit integer is -128 through +127; 16-bit integers may range from -32,768through +32,767; 32-bit integers may range from -2^(31) through +2^(31) -1.The value zero has a positive sign.<DT>Ordinal:<DD>An unsigned binary numeric value contained in a 32-bit doubleword,16-bit word, or 8-bit byte. All bits are considered in determiningmagnitude of the number. The value range of an 8-bit ordinal numberis 0-255; 16 bits can represent values from 0 through 65,535; 32 bitscan represent values from 0 through 2^(32) -1.<DT>Near Pointer:<DD>A 32-bit logical address. A near pointer is an offset within a segment.Near pointers are used in either a flat or a segmented model of memoryorganization.<DT>Far Pointer:<DD>A 48-bit logical address of two components: a 16-bit segment selectorcomponent and a 32-bit offset component. Far pointers are used byapplications programmers only when systems designers choose asegmented memory organization.<DT>String:<DD>A contiguous sequence of bytes, words, or doublewords. A string maycontain from zero bytes to 2^(32) -1 bytes (4 gigabytes).<DT>Bit field:<DD>A contiguous sequence of bits. A bit field may begin at any bit positionof any byte and may contain up to 32 bits.<DT>Bit string:<DD>A contiguous sequence of bits. A bit string may begin at any bit positionof any byte and may contain up to 2^(32) -1 bits.<DT>BCD:<DD>A byte (unpacked) representation of a decimal digit in the range 0 through 9.Unpacked decimal numbers are stored as unsigned byte quantities. Onedigit is stored in each byte. The magnitude of the number is determined fromthe low-order half-byte; hexadecimal values 0-9 are valid and areinterpreted as decimal numbers. The high-order half-byte must be zero formultiplication and division; it may contain any value for addition andsubtraction.<DT>Packed BCD:<DD>A byte (packed) representation of two decimal digits, each in the range0 through 9. One digit is stored in each half-byte. The digit in thehigh-order half-byte is the most significant. Values 0-9 are valid in eachhalf-byte. The range of a packed decimal byte is 0-99.</DL><A HREF="#fig2-4">Figure 2-4</A>  graphically summarizes the data types supported by the 80386.<P><A NAME="fig2-1"><IMG align=center SRC="fig2-1.gif" border=0><P><HR><P><A NAME="fig2-2"><IMG align=center SRC="fig2-2.gif" border=0><P><HR><P><A NAME="fig2-3"><IMG align=center SRC="fig2-3.gif" border=0><P><HR><P><A NAME="fig2-4"><IMG align=center SRC="fig2-4.gif" border=0><P><HR><P><B>up:</B> <A HREF="c02.htm">Chapter 2 -- Basic Programming Model</A><BR><B>prev:</B> <A HREF="s02_01.htm">2.1  Memory Organization and Segmentation</A><BR><B>next:</B> <A HREF="s02_03.htm">2.3  Registers</A></BODY>

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