📄 s15_03.htm
字号:
<!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN"><HTML><HEAD><TITLE>80386 Programmer's Reference Manual -- Section 15.3</TITLE></HEAD><BODY><B>up:</B> <A HREF="c15.htm">Chapter 15 -- Virtual 8086 Mode</A><BR><B>prev:</B> <A HREF="s15_02.htm">15.2 Structure of a V86 Task</A><BR><B>next:</B> <A HREF="s15_04.htm">15.4 Additional Sensitive Instructions</A><P><HR><P><H1>15.3 Entering and Leaving V86 Mode</H1><A HREF="#fig15-2">Figure 15-2</A> summarizes the ways that the processor can enter and leave an8086 program. The processor can enter V86 by either of two means:<OL><LI> A task switch to an 80386 task loads the image of EFLAGS from the newTSS. The TSS of the new task must be an 80386 TSS, not an 80286 TSS,because the 80286 TSS does not store the high-order word of EFLAGS,which contains the VM flag. A value of one in the VM bit of the newEFLAGS indicates that the new task is executing 8086 instructions;therefore, while loading the segment registers from the TSS, theprocessor forms base addresses as the 8086 would.<LI> An <A HREF="IRET.htm">IRET</A> from a procedure of an 80386 task loads the image of EFLAGSfrom the stack. A value of one in VM in this case indicates that theprocedure to which control is being returned is an 8086 procedure. TheCPL at the time the <A HREF="IRET.htm">IRET</A> is executed must be zero, else the processordoes not change VM.</OL>The processor leaves V86 mode when an interrupt or exception occurs. Thereare two cases:<OL><LI> The interrupt or exception causes a task switch. A task switch from aV86 task to any other task loads EFLAGS from the TSS of the new task.If the new TSS is an 80386 TSS and the VM bit in the EFLAGS image iszero or if the new TSS is an 80286 TSS, then the processor clears theVM bit of EFLAGS, loads the segment registers from the new TSS using80386-style address formation, and begins executing the instructionsof the new task according to 80386 protected-mode semantics.<LI> The interrupt or exception vectors to a privilege-level zeroprocedure. The processor stores the current setting of EFLAGS on thestack, then clears the VM bit. The interrupt or exception handler,therefore, executes as "native" 80386 protected-mode code. If aninterrupt or exception vectors to a conforming segment or to aprivilege level other than three, the processor causes ageneral-protection exception; the error code is the selector of theexecutable segment to which transfer was attempted.</OL>Systems software does not manipulate the VM flag directly, but rathermanipulates the image of the EFLAGS register that is stored on the stack orin the TSS. The V86 monitor sets the VM flag in the EFLAGS image on thestack or in the TSS when first creating a V86 task. Exception and interrupthandlers can examine the VM flag on the stack. If the interrupted procedurewas executing in V86 mode, the handler may need to invoke the V86 monitor.<P><A NAME="fig15-2"><IMG align=center SRC="fig15-2.gif" border=0><H2>15.3.1 Transitions Through Task Switches</H2>A task switch to or from a V86 task may be due to any of three causes:<OL><LI> An interrupt that vectors to a task gate.<LI> An action of the scheduler of the 80386 operating system.<LI> An <A HREF="IRET.htm">IRET</A> when the NT flag is set.</OL>In any of these cases, the processor changes the VM bit in EFLAGS accordingto the image of EFLAGS in the new TSS. If the new TSS is an 80286 TSS, thehigh-order word of EFLAGS is not in the TSS; the processor clears VM in thiscase. The processor updates VM prior to loading the segment registers fromthe images in the new TSS. The new setting of VM determines whether theprocessor interprets the new segment-register images as 8086 selectors or80386/80286 selectors.<H2>15.3.2 Transitions Through Trap Gates and Interrupt Gates</H2>The processor leaves V86 mode as the result of an exception or interruptthat vectors via a trap or interrupt gate to a privilege-level zeroprocedure. The exception or interrupt handler returns to the 8086 code byexecuting an <A HREF="IRET.htm">IRET</A>.<P>Because it was designed for execution by an 8086 processor, an 8086 programin a V86 task will have an 8086-style interrupt table starting at linearaddress zero. However, the 80386 does not use this table directly. For allexceptions and interrupts that occur in V86 mode, the processor vectorsthrough the IDT. The IDT entry for an interrupt or exception that occurs ina V86 task must contain either:<UL><LI> A task gate.<LI> An 80386 trap gate (type 14) or an 80386 interrupt gate (type 15),which must point to a nonconforming, privilege-level zero, codesegment.</UL>Interrupts and exceptions that have 80386 trap or interrupt gates in theIDT vector to the appropriate handler procedure at privilege-level zero. Thecontents of all the 8086 segment registers are stored on the PL 0 stack.<A HREF="#fig15-3">Figure 15-3</A> shows the format of the PL 0 stack after an exception orinterrupt that occurs while a V86 task is executing an 8086 program.<P>After the processor stores all the 8086 segment registers on the PL 0stack, it loads all the segment registers with zeros before starting toexecute the handler procedure. This permits the interrupt handler to safelysave and restore the DS, ES, FS, and GS registers as 80386 selectors.Interrupt handlers that may be invoked in the context of either a regulartask or a V86 task, can use the same prolog and epilog code for registersaving regardless of the kind of task. Restoring zeros to these registersbefore execution of the <A HREF="IRET.htm">IRET</A> does not cause a trap in the interrupt handler.Interrupt procedures that expect values in the segment registers or thatreturn values via segment registers have to use the register images storedon the PL 0 stack. Interrupt handlers that need to know whether theinterrupt occurred in V86 mode can examine the VM bit in the stored EFLAGSimage.<P>An interrupt handler passes control to the V86 monitor if the VM bit is setin the EFLAGS image stored on the stack and the interrupt or exception isone that the monitor needs to handle. The V86 monitor may either:<UL><LI> Handle the interrupt completely within the V86 monitor.<LI> Invoke the 8086 program's interrupt handler.</UL><P>Reflecting an interrupt or exception back to the 8086 code involves thefollowing steps:<OL><LI> Refer to the 8086 interrupt vector to locate the appropriate handlerprocedure.<LI> Store the state of the 8086 program on the privilege-level threestack.<LI> Change the return link on the privilege-level zero stack to point tothe privilege-level three handler procedure.<LI> Execute an <A HREF="IRET.htm">IRET</A> so as to pass control to the handler.<LI> When the <A HREF="IRET.htm">IRET</A> by the privilege-level three handler again traps to theV86 monitor, restore the return link on the privilege-level zero stackto point to the originally interrupted, privilege-level threeprocedure.<LI> Execute an <A HREF="IRET.htm">IRET</A> so as to pass control back to the interruptedprocedure.</OL><A NAME="fig15-3"><IMG align=center SRC="fig15-3.gif" border=0><P><HR><P><B>up:</B> <A HREF="c15.htm">Chapter 15 -- Virtual 8086 Mode</A><BR><B>prev:</B> <A HREF="s15_02.htm">15.2 Structure of a V86 Task</A><BR><B>next:</B> <A HREF="s15_04.htm">15.4 Additional Sensitive Instructions</A></BODY>⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -