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<!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN"><HTML><HEAD><TITLE>80386 Programmer's Reference Manual -- Section 8.3</TITLE></HEAD><BODY><B>up:</B> <A HREF="c08.htm">Chapter 8 -- Input/Output</A><BR><B>prev:</B> <A HREF="s08_02.htm">8.2 I/O Instructions</A><BR><B>next:</B> <A HREF="c09.htm">Chapter 9 -- Exceptions and Interrupts</A><P><HR><P><H1>8.3 Protection and I/O</H1>Two mechanisms provide protection for I/O functions:<OL><LI> The IOPL field in the EFLAGS register defines the right to useI/O-related instructions.<LI> The I/O permission bit map of a 80386 TSS segment defines the rightto use ports in the I/O address space.</OL>These mechanisms operate only in protected mode, including virtual 8086mode; they do not operate in real mode. In real mode, there is no protectionof the I/O space; any procedure can execute I/O instructions, and any I/Oport can be addressed by the I/O instructions.<H2>8.3.1 I/O Privilege Level</H2>Instructions that deal with I/O need to be restricted but also need to beexecuted by procedures executing at privilege levels other than zero. Forthis reason, the processor uses two bits of the flags register to store theI/O privilege level (IOPL). The IOPL defines the privilege levelneeded to execute I/O-related instructions.<P>The following instructions can be executed only if CPL <= IOPL:<UL><LI> <A HREF="IN.htm">IN</A> -- Input<LI> <A HREF="INS.htm">INS</A> -- Input String<LI> <A HREF="OUT.htm">OUT</A> -- Output<LI> <A HREF="OUTS.htm">OUTS</A> -- Output String<LI> <A HREF="CLI.htm">CLI</A> -- Clear Interrupt-Enable Flag<LI> <A HREF="STI.htm">STI</A> -- Set Interrupt-Enable</UL>These instructions are called "sensitive" instructions, because they aresensitive to IOPL.<P>To use sensitive instructions, a procedure must execute at a privilegelevel at least as privileged as that specified by the IOPL (CPL <= IOPL). Anyattempt by a less privileged procedure to use a sensitive instructionresults in a general protection exception.<P>Because each task has its own unique copy of the flags register, each taskcan have a different IOPL. A task whose primary function is to perform I/O(a device driver) can benefit from having an IOPL of three, therebypermitting all procedures of the task to perform I/O. Other tasks typicallyhave IOPL set to zero or one, reserving the right to perform I/Oinstructions for the most privileged procedures.<P>A task can change IOPL only with the <A HREF="POPF.htm">POPF</A> instruction; however, suchchanges are privileged. No procedure may alter IOPL (the I/O privilege levelin the flag register) unless the procedure is executing at privilege level0. An attempt by a less privileged procedure to alter IOPL does not resultin an exception; IOPL simply remains unaltered.<P>The <A HREF="POPF.htm">POPF</A> instruction may be used in addition to <A HREF="CLI.htm">CLI</A> and <A HREF="STI.htm">STI</A> to alter theinterrupt-enable flag (IF); however, changes to IF by <A HREF="POPF.htm">POPF</A> areIOPL-sensitive. A procedure may alter IF with a <A HREF="POPF.htm">POPF</A> instruction only whenexecuting at a level that is at least as privileged as IOPL. An attempt by aless privileged procedure to alter IF in this manner does not result in anexception; IF simply remains unaltered.<H2>8.3.2 I/O Permission Bit Map</H2>The I/O instructions that directly refer to addresses in the processor'sI/O space are <A HREF="IN.htm">IN</A>, <A HREF="INS.htm">INS</A>, <A HREF="OUT.htm">OUT</A>, <A HREF="OUTS.htm">OUTS</A>. The 80386 has the ability to selectivelytrap references to specific I/O addresses. The structure that enablesselective trapping is the I/O Permission Bit Map in the TSS segment (see<A HREF="#fig8-2">Figure 8-2</A>). The I/O permission map is a bit vector. The size of the mapand its location in the TSS segment are variable. The processor locates theI/O permission map by means of the I/O map base field in the fixed portionof the TSS. The I/O map base field is 16 bits wide and contains the offsetof the beginning of the I/O permission map. The upper limit of the I/Opermission map is the same as the limit of the TSS segment.<P>In protected mode, when it encounters an I/O instruction (<A HREF="IN.htm">IN</A>, <A HREF="INS.htm">INS</A>, <A HREF="OUT.htm">OUT</A>, or<A HREF="OUTS.htm">OUTS</A>), the processor first checks whether CPL <= IOPL. If this condition istrue, the I/O operation may proceed. If not true, the processor checks theI/O permission map. (In virtual 8086 mode, the processor consults the mapwithout regard for IOPL . Refer to <A HREF="c15.htm">Chapter 15</A>.)<P>Each bit in the map corresponds to an I/O port byte address; for example,the bit for port 41 is found at I/O map base + 5, bit offset 1. Theprocessor tests all the bits that correspond to the I/O addresses spanned byan I/O operation; for example, a doubleword operation tests four bitscorresponding to four adjacent byte addresses. If any tested bit is set,the processor signals a general protection exception. If all the tested bitsare zero, the I/O operation may proceed.<P>It is not necessary for the I/O permission map to represent all the I/Oaddresses. I/O addresses not spanned by the map are treated as if they hadone bits in the map. For example, if TSS limit is equal to I/O map base +31, the first 256 I/O ports are mapped; I/O operations on any port greaterthan 255 cause an exception.<P>If I/O map base is greater than or equal to TSS limit, the TSS segment hasno I/O permission map, and all I/O instructions in the 80386 program causeexceptions when CPL > IOPL.<P>Because the I/O permission map is in the TSS segment, different tasks canhave different maps. Thus, the operating system can allocate ports to a taskby changing the I/O permission map in the task's TSS.<P><A NAME="fig8-2"><IMG align=center SRC="fig8-2.gif" border=0><P><HR><P><B>up:</B> <A HREF="c08.htm">Chapter 8 -- Input/Output</A><BR><B>prev:</B> <A HREF="s08_02.htm">8.2 I/O Instructions</A><BR><B>next:</B> <A HREF="c09.htm">Chapter 9 -- Exceptions and Interrupts</A></BODY>⌨️ 快捷键说明
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