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<!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN"><HTML><HEAD><TITLE>80386 Programmer's Reference Manual -- Opcode SHRD</TITLE></HEAD><BODY><B>up:</B> <A HREF="c17.htm">Chapter 17 -- 80386 Instruction Set</A><BR><B>prev:</B><A HREF="SHLD.htm"> SHLD Double Precision Shift Left</A><BR><B>next:</B><A HREF="SLDT.htm"> SLDT Store Local Descriptor Table Register</A><P><HR><P><H1>SHRD -- Double Precision Shift Right</H1><PRE>Opcode Instruction Clocks Description0F AC SHRD r/m16,r16,imm8 3/7 r/m16 gets SHR of r/m16 concatenated with r160F AC SHRD r/m32,r32,imm8 3/7 r/m32 gets SHR of r/m32 concatenated with r320F AD SHRD r/m16,r16,CL 3/7 r/m16 gets SHR of r/m16 concatenated with r160F AD SHRD r/m32,r32,CL 3/7 r/m32 gets SHR of r/m32 concatenated with r32</PRE><H2>Operation</H2><PRE>(* count is an unsigned integer corresponding to the last operand of theinstruction, either an immediate byte or the byte in register CL *)ShiftAmt := count MOD 32;inBits := register; (* Allow overlapped operands *)IF ShiftAmt = 0THEN no operationELSE IF ShiftAmt >= OperandSize THEN (* Bad parameters *) r/m := UNDEFINED; CF, OF, SF, ZF, AF, PF := UNDEFINED; ELSE (* Perform the shift *) CF := BIT[r/m, ShiftAmt - 1]; (* last bit shifted out on exit *) FOR i := 0 TO OperandSize - 1 - ShiftAmt DO BIT[r/m, i] := BIT[r/m, i - ShiftAmt]; OD; FOR i := OperandSize - ShiftAmt TO OperandSize - 1 DO BIT[r/m,i] := BIT[inBits,i+ShiftAmt - OperandSize]; OD; Set SF, ZF, PF (r/m); (* SF, ZF, PF are set according to the value of the result *) Set SF, ZF, PF (r/m); AF := UNDEFINED; FI;FI;</PRE><H2>Description</H2>SHRD shifts the first operand provided by the r/m field to the right as manybits as specified by the count operand. The second operand (r16 or r32)provides the bits to shift in from the left (starting with bit 31). Theresult is stored back into the r/m operand. The register remains unaltered.<P>The count operand is provided by either an immediate byte or the contentsof the CL register. These operands are taken MODULO 32 to provide a numberbetween 0 and 31 by which to shift. Because the bits to shift are providedby the specified register, the operation is useful for multi-precisionshifts (64 bits or more). The SF, ZF and PF flags are set according to thevalue of the result. CS is set to the value of the last bit shifted out. OFand AF are left undefined.<H2>Flags Affected</H2>OF, SF, ZF, PF, and CF as described above; AF and OF are undefined<H2>Protected Mode Exceptions</H2>#GP(0) if the result is in a nonwritable segment; #GP(0) for an illegalmemory operand effective address in the CS, DS, ES, FS, or GSsegments; #SS(0) for an illegal address in the SS segment; #PF(fault-code)for a page fault<H2>Real Address Mode Exceptions</H2>Interrupt 13 if any part of the operand would lie outside of the effectiveaddress space from 0 to 0FFFFH<H2>Virtual 8086 Mode Exceptions</H2>Same exceptions as in Real Address Mode; #PF(fault-code) for a pagefault<P><HR><P><B>up:</B> <A HREF="c17.htm">Chapter 17 -- 80386 Instruction Set</A><BR><B>prev:</B><A HREF="SHLD.htm"> SHLD Double Precision Shift Left</A><BR><B>next:</B><A HREF="SLDT.htm"> SLDT Store Local Descriptor Table Register</A></BODY>⌨️ 快捷键说明
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