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<!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN"><HTML><HEAD><TITLE>80386 Programmer's Reference Manual -- Section 5.1</TITLE></HEAD><BODY><B>up:</B> <A HREF="c05.htm">Chapter 5 -- Memory Management</A><BR><B>prev:</B> <A HREF="c05.htm">Chapter 5 -- Memory Management</A><BR> <B>next:</B> <A HREF="s05_02.htm">5.2 Page Translation</A><P><HR><P><H1>5.1 Segment Translation</H1><A HREF="#fig5-2">Figure 5-2</A> shows in more detail how the processor converts a logicaladdress into a linear address.<P>To perform this translation, the processor uses the following datastructures:<UL><LI> Descriptors<LI> Descriptor tables<LI> Selectors<LI> Segment Registers</UL><H2>5.1.1 Descriptors</H2>The segment descriptor provides the processor with the data it needs to mapa logical address into a linear address. Descriptors are created bycompilers, linkers, loaders, or the operating system, not by applicationsprogrammers. <A HREF="#fig5-3">Figure 5-3</A> illustrates the two general descriptor formats. Alltypes of segment descriptors take one of these formats. Segment-descriptorfields are:<P>BASE: Defines the location of the segment within the 4 gigabyte linearaddress space. The processor concatenates the three fragments of the baseaddress to form a single 32-bit value.<P>LIMIT: Defines the size of the segment. When the processor concatenates thetwo parts of the limit field, a 20-bit value results. The processorinterprets the limit field in one of two ways, depending on the setting ofthe granularity bit:<OL><LI> In units of one byte, to define a limit of up to 1 megabyte.<LI> In units of 4 Kilobytes, to define a limit of up to 4 gigabytes. Thelimit is shifted left by 12 bits when loaded, and low-order one-bitsare inserted.</OL>Granularity bit: Specifies the units with which the LIMIT field isinterpreted. When thebit is clear, the limit is interpreted in units of onebyte; when set, the limit is interpreted in units of 4 Kilobytes.<P>TYPE: Distinguishes between various kinds of descriptors.<P>DPL (Descriptor Privilege Level): Used by the protection mechanism (referto <A HREF="c06.htm">Chapter 6</A> ) .<P>Segment-Present bit: If this bit is zero, the descriptor is not valid foruse in address transformation; the processor will signal an exception when aselector for the descriptor is loaded into a segment register. <A HREF="#fig5-4">Figure 5-4</A> shows the format of a descriptor when the present-bit is zero. The operatingsystem is free to use the locations marked AVAILABLE. Operating systems thatimplement segment-based virtual memory clear the present bit in either ofthese cases:<UL><LI> When the linear space spanned by the segment is not mapped by thepaging mechanism.<LI> When the segment is not present in memory.</UL>Accessed bit: The processor sets this bit when the segment is accessed;i.e., a selector for the descriptor is loaded into a segment register orused by a selector test instruction. Operating systems that implementvirtual memory at the segment level may, by periodically testing andclearing this bit, monitor frequency of segment usage.<P>Creation and maintenance of descriptors is the responsibility of systemssoftware, usually requiring the cooperation of compilers, program loaders orsystem builders, and therating system.<P><A NAME="fig5-2"><IMG align=center SRC="fig5-2.gif" border=0><P><HR><P><A NAME="fig5-3"><IMG align=center SRC="fig5-3.gif" border=0><P><H2>5.1.2 Descriptor Tables</H2>Segment descriptors are stored in either of two kinds of descriptor table:<UL><LI> The global descriptor table (GDT)<LI> A local descriptor table (LDT)</UL>A descriptor table is simply a memory array of 8-byte entries that containdescriptors, as <A HREF="#fig5-5">Figure 5-5</A> shows. A descriptor table is variable in lengthand may contain up to 8192 (2^(13)) descriptors. The first entry of the GDT(INDEX=0) is not used by the processor, however.<P>The processor locates the GDT and the current LDT in memory by means of theGDTR and LDTR registers. These registers store the base addresses of thetables in the linear address space and store the segment limits. Theinstructions <A HREF="LGDT.htm">LGDT</A> and <A HREF="SGDT.htm">SGDT</A> give access to the GDTR; the instructions <A HREF="LLDT.htm">LLDT</A>and <A HREF="SLDT.htm">SLDT</A> give access to the LDTR.<P><A NAME="fig5-4"><IMG align=center SRC="fig5-4.gif" border=0><P><HR><P><A NAME="fig5-5"><IMG align=center SRC="fig5-5.gif" border=0><P><H2>5.1.3 Selectors</H2>The selector portion of a logical address identifies a descriptor byspecifying a descriptor table and indexing a descriptor within that table.Selectors may be visible to applications programs as a field within apointer variable, but the values of selectors are usually assigned (fixedup) by linkers or linking loaders. <A HREF="#fig5-6">Figure 5-6</A> shows the format of aselector.<P>Index: Selects one of 8192 descriptors in a descriptor table. The processorsimply multiplies this index value by 8 (the length of a descriptor), andadds the result to the base address of the descriptor table in order toaccess the appropriate segment descriptor in the table.<P>Table Indicator: Specifies to which descriptor table the selector refers. Azero indicates the GDT; a one indicates the current LDT.<P>Requested Privilege Level: Used by the protection mechanism. (Refer to<A HREF="c06.htm">Chapter 6</A>)<P>Because the first entry of the GDT is not used by the processor, a selectorthat has an index of zero and a table indicator of zero (i.e., a selectorthat points to the first entry of the GDT), can be used as a null selector.The processor does not cause an exception when a segment register (otherthan CS or SS) is loaded with a null selector. It will, however, cause anexception when the segment register is used to access memory. This featureis useful for initializing unused segment registers so as to trap accidentalreferences.<P><A NAME="fig5-6"><IMG align=center SRC="fig5-6.gif" border=0><P><HR><P><A NAME="fig5-7"><IMG align=center SRC="fig5-7.gif" border=0><P><H2>5.1.4 Segment Registers</H2>The 80386 stores information from descriptors in segment registers, therebyavoiding the need to consult a descriptor table every time it accessesmemory.<P>Every segment register has a "visible" portion and an "invisible" portion,as <A HREF="#fig5-7">Figure 5-7</A> illustrates. The visible portions of these segment addressregisters are manipulated by programs as if they were simply 16-bitregisters. The invisible portions are manipulated by the processor.<P>The operations that load these registers are normal program instructions(previously described in <A HREF="c03.htm">Chapter 3</A>). These instructions are of two classes:<OL><LI> Direct load instructions; for example, <A HREF="MOV.htm">MOV</A>, <A HREF="POP.htm">POP</A>, <A HREF="LGS.htm">LDS</A>, <A HREF="LGS.htm">LSS</A>, <A HREF="LGS.htm">LGS</A>, <A HREF="LGS.htm">LFS</A>.These instructions explicitly reference the segment registers.<LI> Implied load instructions; for example, far <A HREF="CALL.htm">CALL</A> and <A HREF="JMP.htm">JMP</A>. Theseinstructions implicitly reference the CS register, and load it with anew value.</OL>Using these instructions, a program loads the visible part of the segmentregister with a 16-bit selector. The processor automatically fetches thebase address, limit, type, and other information from a descriptor table andloads them into the invisible part of the segment register.<P>Because most instructions refer to data in segments whose selectors havealready been loaded into segment registers, the processor can add thesegment-relative offset supplied by the instruction to the segment baseaddress with no additional overhead.<P><HR><P><B>up:</B> <A HREF="c05.htm">Chapter 5 -- Memory Management</A><BR><B>prev:</B> <A HREF="c05.htm">Chapter 5 -- Memory Management</A><BR> <B>next:</B> <A HREF="s05_02.htm">5.2 Page Translation</A></BODY>⌨️ 快捷键说明
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