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📄 s07_01.htm

📁 Programmer s Reference Manual is an improtant book on Intel processor architecture and programming.
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<!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN"><HTML><HEAD><TITLE>80386 Programmer's Reference Manual -- Section 7.1</TITLE></HEAD><BODY><B>up:</B> <A HREF="c07.htm">Chapter 7 -- Multitasking</A><BR><B>prev:</B> <A HREF="c07.htm">Chapter 7 -- Multitasking</A><BR><B>next:</B> <A HREF="s07_02.htm">7.2  TSS Descriptor</A><P><HR><P><H1>7.1  Task State Segment</H1>All the information the processor needs in order to manage a task is storedin a special type of segment, a task state segment (TSS). <A HREF="#fig7-1">Figure 7-1</A>  showsthe format of a TSS for executing 80386 tasks. (Another format is used forexecuting 80286 tasks; refer to <A HREF="c13.htm">Chapter 13</A>.)<P>The fields of a TSS belong to two classes:<OL><LI> A dynamic set that the processor updates with each switch from thetask. This set includes the fields that store:<UL><LI> The general registers (EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI).<LI> The segment registers (ES, CS, SS, DS, FS, GS).<LI> The flags register (EFLAGS).<LI> The instruction pointer (EIP).<LI> The selector of the TSS of the previously executing task (updatedonly when a return is expected).</UL><LI> A static set that the processor reads but does not change. This setincludes the fields that store:<UL><LI> The selector of the task's LDT.<LI> The register (PDBR) that contains the base address of the task'spage directory (read only when paging is enabled).<LI> Pointers to the stacks for privilege levels 0-2.<LI> The T-bit (debug trap bit) which causes the processor to raise adebug exception when a task switch occurs . (Refer to <A HREF="c12.htm">Chapter 12</A>  for more information on debugging.)<LI> The I/O map base (refer to <A HREF="c08.htm">Chapter 8</A> for more information on theuse of the I/O map).</UL></OL>Task state segments may reside anywhere in the linear space. The only casethat requires caution is when the TSS spans a page boundary and thehigher-addressed page is not present. In this case, the processor raises anexception if it encounters the not-present page while reading the TSS duringa task switch. Such an exception can be avoided by either of two strategies:<OL><LI> By allocating the TSS so that it does not cross a page boundary.<LI> By ensuring that both pages are either both present or bothnot-present at the time of a task switch. If both pages arenot-present, then the page-fault handler must make both pages presentbefore restarting the instruction that caused the task switch.</OL><A NAME="fig7-1"><IMG align=center SRC="fig7-1.gif" border=0><P><HR><P><B>up:</B> <A HREF="c07.htm">Chapter 7 -- Multitasking</A><BR><B>prev:</B> <A HREF="c07.htm">Chapter 7 -- Multitasking</A><BR><B>next:</B> <A HREF="s07_02.htm">7.2  TSS Descriptor</A></BODY>

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