📄 s02_03.htm
字号:
<!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN"><HTML><HEAD><TITLE>80386 Programmer's Reference Manual -- Section 2.3</TITLE></HEAD><BODY><B>up:</B> <A HREF="c02.htm">Chapter 2 -- Basic Programming Model</A><BR><B>prev:</B> <A HREF="s02_02.htm">2.2 Data Types</A><BR><B>next:</B> <A HREF="s02_04.htm">2.4 Instruction Format</A><P><HR><P><H1>2.3 Registers</H1>The 80386 contains a total of sixteen registers that are of interest to theapplications programmer. As <A HREF="#fig2-5">Figure 2-5</A> shows, these registers may begrouped into these basic categories:<OL><LI>General registers. These eight 32-bit general-purpose registers areused primarily to contain operands for arithmetic and logicaloperations.<LI>Segment registers. These special-purpose registers permit systemssoftware designers to choose either a flat or segmented model ofmemory organization. These six registers determine, at any given time,which segments of memory are currently addressable.<LI>Status and instruction registers. These special-purpose registers areused to record and alter certain aspects of the 80386 processor state.</OL><H2>2.3.1 General Registers</H2>The general registers of the 80386 are the 32-bit registers EAX, EBX, ECX,EDX, EBP, ESP, ESI, and EDI. These registers are used interchangeably tocontain the operands of logical and arithmetic operations. They may also beused interchangeably for operands of address computations (except that ESPcannot be used as an index operand).<P>As <A HREF="#fig2-5">Figure 2-5</A> shows, the low-order word of each of these eight registershas a separate name and can be treated as a unit. This feature is useful forhandling 16-bit data items and for compatibility with the 8086 and 80286processors. The word registers are named AX, BX, CX, DX, BP, SP, SI, and DI.<P><A HREF="#fig2-5">Figure 2-5</A> also illustrates that each byte of the 16-bit registers AX, BX,CX, and DX has a separate name and can be treated as a unit. This feature isuseful for handling characters and other 8-bit data items. The byteregisters are named AH, BH, CH, and DH (high bytes); and AL, BL, CL, and DL(low bytes).<P>All of the general-purpose registers are available for addressingcalculations and for the results of most arithmetic and logicalcalculations; however, a few functions are dedicated to certain registers.By implicitly choosing registers for these functions, the 80386 architecturecan encode instructions more compactly. The instructions that use specificregisters include: double-precision multiply and divide, I/O, stringinstructions, translate, loop, variable shift and rotate, and stackoperations.<H2>2.3.2 Segment Registers</H2>The segment registers of the 80386 give systems software designers theflexibility to choose among various models of memory organization.Implementation of memory models is the subject of Part II -- SystemsProgramming. Designers may choose a model in which applications programs donot need to modify segment registers, in which case applications programmersmay skip this section.<P>Complete programs generally consist of many different modules, eachconsisting of instructions and data. However, at any given time duringprogram execution, only a small subset of a program's modules are actuallyin use. The 80386 architecture takes advantage of this by providingmechanisms to support direct access to the instructions and data of thecurrent module's environment, with access to additional segments on demand.<P>At any given instant, six segments of memory may be immediately accessibleto an executing 80386 program. The segment registers CS, DS, SS, ES, FS, andGS are used to identify these six current segments. Each of these registersspecifies a particular kind of segment, as characterized by the associatedmnemonics ("code," "data," or "stack") shown in <A HREF="#fig2-6">Figure 2-6</A> . Each registeruniquely determines one particular segment, from among the segments thatmake up the program, that is to be immediately accessible at highest speed.<P>The segment containing the currently executing sequence of instructions isknown as the current code segment; it is specified by means of the CSregister. The 80386 fetches all instructions from this code segment, usingas an offset the contents of the instruction pointer. CS is changedimplicitly as the result of intersegment control-transfer instructions (forexample, <A HREF="CALL.htm">CALL</A> and <A HREF="JMP.html">JMP</A>), interrupts, and exceptions.<P>Subroutine calls, parameters, and procedure activation records usuallyrequire that a region of memory be allocated for a stack. All stackoperations use the SS register to locate the stack. Unlike CS, the SSregister can be loaded explicitly, thereby permitting programmers to definestacks dynamically.<P>The DS, ES, FS, and GS registers allow the specification of four datasegments, each addressable by the currently executing program. Accessibilityto four separate data areas helps programs efficiently access differenttypes of data structures; for example, one data segment register can pointto the data structures of the current module, another to the exported dataof a higher-level module, another to a dynamically created data structure,and another to data shared with another task. An operand within a datasegment is addressed by specifying its offset either directly in aninstruction or indirectly via general registers.<P>Depending on the structure of data (e.g., the way data is parceled into oneor more segments), a program may require access to more than four datasegments. To access additional segments, the DS, ES, FS, and GS registerscan be changed under program control during the course of a program'sexecution. This simply requires that the program execute an instruction toload the appropriate segment register prior to executing instructions thataccess the data.<P>The processor associates a base address with each segment selected by asegment register. To address an element within a segment, a 32-bit offset isadded to the segment's base address. Once a segment is selected (by loadingthe segment selector into a segment register), a data manipulationinstruction only needs to specify the offset. Simple rules define whichsegment register is used to form an address when only an offset isspecified.<P><A NAME="fig2-5"><IMG align=center SRC="fig2-5.gif" border=0><P><HR><P><A NAME="fig2-6"><IMG align=center SRC="fig2-6.gif" border=0><P><H2>2.3.3 Stack Implementation</H2>Stack operations are facilitated by three registers:<OL><LI>The stack segment (SS) register. Stacks are implemented in memory. Asystem may have a number of stacks that is limited only by the maximumnumber of segments. A stack may be up to 4 gigabytes long, the maximumlength of a segment. One stack is directly addressable at a --one located by SS. This is the current stack, often referred to simplyas "the" stack. SS is used automatically by the processor for allstack operations.<LI>The stack pointer (ESP) register. ESP points to the top of thepush-down stack (TOS). It is referenced implicitly by <A HREF="PUSH.htm">PUSH</A> and <A HREF="POP.html">POP</A>operations, subroutine calls and returns, and interrupt operations.When an item is pushed onto the stack (see <A HREF="#fig2-7">Figure 2-7</A> ), the processordecrements ESP, then writes the item at the new TOS. When an item ispopped off the stack, the processor copies it from TOS, thenincrements ESP. In other words, the stack grows down in memory towardlesser addresses.<LI>The stack-frame base pointer (EBP) register. The EBP is the bestchoice of register for accessing data structures, variables anddynamically allocated work space within the stack. EBP is often usedto access elements on the stack relative to a fixed point on the stackrather than relative to the current TOS. It typically identifies thebase address of the current stack frame established for the currentprocedure. When EBP is used as the base register in an offsetcalculation, the offset is calculated automatically in the currentstack segment (i.e., the segment currently selected by SS). BecauseSS does not have to be explicitly specified, instruction encoding insuch cases is more efficient. EBP can also be used to index intosegments addressable via other segment registers.</OL> <P><A NAME="fig2-7"><IMG align=center SRC="fig2-7.gif" border=0><P><H2>2.3.4 Flags Register</H2>The flags register is a 32-bit register named EFLAGS. <A HREF="#fig2-8">Figure 2-8</A> definesthe bits within this register. The flags control certain operations andindicate the status of the 80386.<P>The low-order 16 bits of EFLAGS is named FLAGS and can be treated as aunit. This feature is useful when executing 8086 and 80286 code, becausethis part of EFLAGS is identical to the FLAGS register of the 8086 and the80286.<P>The flags may be considered in three groups: the status flags, the controlflags, and the systems flags. Discussion of the systems flags is delayeduntil Part II.<P><A NAME="fig2-8"><IMG align=center SRC="fig2-8.gif" border=0><P><H3>2.3.4.1 Status Flags</H3>The status flags of the EFLAGS register allow the results of oneinstruction to influence later instructions. The arithmetic instructions useOF, SF, ZF, AF, PF, and CF. The SCAS (Scan String), <A HREF="CMPS.htm">CMPS</A> (Compare String),and <A HREF="LOOP.htm">LOOP</A> instructions use ZF to signal that their operations are complete.There are instructions to set, clear, and complement CF before execution ofan arithmetic instruction. Refer to <A HREF="appc.htm">Appendix C</A> for definition of eachstatus flag.<H3>2.3.4.2 Control Flag</H3>The control flag DF of the EFLAGS register controls string instructions.DF (Direction Flag, bit 10)Setting DF causes string instructions to auto-decrement; that is, toprocess strings from high addresses to low addresses. Clearing DF causesstring instructions to auto-increment, or to process strings from lowaddresses to high addresses.<H3>2.3.4.3 Instruction Pointer</H3>The instruction pointer register (EIP) contains the offset address,relative to the start of the current code segment, of the next sequentialinstruction to be executed. The instruction pointer is not directly visibleto the programmer; it is controlled implicitly by control-transferinstructions, interrupts, and exceptions.<P>As <A HREF="#fig2-9">Figure 2-9</A> shows, the low-order 16 bits of EIP is named IP and can beused by the processor as a unit. This feature is useful when executinginstructions designed for the 8086 and 80286 processors.<P><A NAME="fig2-9"><IMG align=center SRC="fig2-9.gif" border=0><P><HR><P><B>up:</B> <A HREF="c02.htm">Chapter 2 -- Basic Programming Model</A><BR><B>prev:</B> <A HREF="s02_02.htm">2.2 Data Types</A><BR><B>next:</B> <A HREF="s02_04.htm">2.4 Instruction Format</A></BODY>⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -