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<!DOCTYPE HTML PUBLIC "-//IETF//DTD HTML 2.0//EN"><HTML><HEAD><TITLE>80386 Programmer's Reference Manual -- Section 12.3</TITLE></HEAD><BODY><B>up:</B> <A HREF="c12.htm">Chapter 12 -- Debugging</A><BR><B>prev:</B> <A HREF="s12_02.htm">12.2 Debug Registers</A><BR><B>next:</B> <A HREF="c13.htm">Chapter 13 -- Executing 80286 Protected-Mode Code</A><P><HR><P><H1>12.3 Debug Exceptions</H1>Two of the interrupt vectors of the 80386 are reserved for exceptions thatrelate to debugging. Interrupt 1 is the primary means of invoking debuggersdesigned expressly for the 80386; interrupt 3 is intended for debuggingdebuggers and for compatibility with prior processors in Intel's 8086processor family.<H2>12.3.1 Interrupt 1 -- Debug Exceptions</H2>The handler for this exception is usually a debugger or part of a debuggingsystem. The processor causes interrupt 1 for any of several conditions. Thedebugger can check flags in DR6 and DR7 to determine what condition causedthe exception and what other conditions might be in effect at the same time.<A HREF="#Table 12-2">Table 12-2</A> associates with each breakpoint condition the combination ofbits that indicate when that condition has caused the debug exception.<P>Instruction address breakpoint conditions are faults, while other debugconditions are traps. The debug exception may report either or both at onetime. The following paragraphs present details for each class of debugexception.<A NAME="Table 12-2"><PRE>Table 12-2. Debug Exception ConditionsFlags to Test ConditionBS=1 Single-step trapB0=1 AND (GE0=1 OR LE0=1) Breakpoint DR0, LEN0, R/W0B1=1 AND (GE1=1 OR LE1=1) Breakpoint DR1, LEN1, R/W1B2=1 AND (GE2=1 OR LE2=1) Breakpoint DR2, LEN2, R/W2B3=1 AND (GE3=1 OR LE3=1) Breakpoint DR3, LEN3, R/W3BD=1 Debug registers not available; in use by ICE-386.BT=1 Task switch</PRE></A><H3>12.3.1.1 Instruction Addrees Breakpoint</H3>The processor reports an instruction-address breakpoint before it executesthe instruction that begins at the given address; i.e., an instruction-address breakpoint exception is a fault.<P>The RF (restart flag) permits the debug handler to retry instructions thatcause other kinds of faults in addition to debug faults. When it detects afault, the processor automatically sets RF in the flags image that it pushesonto the stack. (It does not, however, set RF for traps and aborts.)<P>When RF is set, it causes any debug fault to be ignored during the nextinstruction. (Note, however, that RF does not cause breakpoint traps to beignored, nor other kinds of faults.)<P>The processor automatically clears RF at the successful completion of everyinstruction except after the <A HREF="IRET.htm">IRET</A> instruction, after the <A HREF="POPF.htm">POPF</A> instruction,and after a <A HREF="JMP.htm">JMP</A>, <A HREF="CALL.htm">CALL</A>, or <A HREF="INT.htm">INT</A> instruction that causes a task switch. Theseinstructions set RF to the value specified by the memory image of the EFLAGSregister.<P>The processor automatically sets RF in the EFLAGS image on the stack beforeentry into any fault handler. Upon entry into the fault handler forinstruction address breakpoints, for example, RF is set in the EFLAGS imageon the stack; therefore, the <A HREF="IRET.htm">IRET</A> instruction at the end of the handler willset RF in the EFLAGS register, and execution will resume at the breakpointaddress without generating another breakpoint fault at the same address.<P>If, after a debug fault, RF is set and the debug handler retries thefaulting instruction, it is possible that retrying the instruction willraise other faults. The retry of the instruction after these faults willalso be done with RF=1, with the result that debug faults continue to beignored. The processor clears RF only after successful completion of theinstruction.<P>Real-mode debuggers can control the RF flag by using a 32-bit <A HREF="IRET.htm">IRET</A>. A16-bit <A HREF="IRET.htm">IRET</A> instruction does not affect the RF bit (which is in thehigh-order 16 bits of EFLAGS). To use a 32-bit <A HREF="IRET.htm">IRET</A>, the debugger mustrearrange the stack so that it holds appropriate values for the 32-bit EIP,CS, and EFLAGS (with RF set in the EFLAGS image). Then executing an <A HREF="IRET.htm">IRET</A>with an operand size prefix causes a 32-bit return, popping the RF flaginto EFLAGS.<H3>12.3.1.2 Data Address Breakpoint</H3>A data-address breakpoint exception is a trap; i.e., the processor reportsa data-address breakpoint after executing the instruction that accesses thegiven memory item.<P>When using data breakpoints it is recommended that either the LE or GE bitof DR7 be set also. If either LE or GE is set, any data breakpoint trap isreported exactly after completion of the instruction that accessed thespecified memory item. This exact reporting is accomplished by forcing the80386 execution unit to wait for completion of data operand transfers beforebeginning execution of the next instruction. If neither GE nor LE is set,data breakpoints may not be reported until one instruction after the data isaccessed or may not be reported at all. This is due to the fact that,normally, instruction execution is overlapped with memory transfers to sucha degree that execution of the next instruction may begin before memorytransfers for the prior instruction are completed.<P>If a debugger needs to preserve the contents of a write breakpointlocation, it should save the original contents before setting a writebreakpoint. Because data breakpoints are traps, a write into a breakpointlocation will complete before the trap condition is reported. The handlercan report the saved value after the breakpoint is triggered. The data inthe debug registers can be used to address the new value stored by theinstruction that triggered the breakpoint.<H3>12.3.1.3 General Detect Fault</H3>This exception occurs when an attempt is made to use the debug registers atthe same time that ICE-386 is using them. This additional protection featureis provided to guarantee that ICE-386 can have full control over thedebug-register resources when required. ICE-386 uses the debug-registers;therefore, a software debugger that also uses these registers cannot runwhile ICE-386 is in use. The exception handler can detect this condition byexamining the BD bit of DR6.<H3>12.3.1.4 Single-Step Trap</H3>This debug condition occurs at the end of an instruction if the trap flag(TF) of the flags register held the value one at the beginning of thatinstruction. Note that the exception does not occur at the end of aninstruction that sets TF. For example, if <A HREF="POPF.htm">POPF</A> is used to set TF, asingle-step trap does not occur until after the instruction that follows<A HREF="POPF.htm">POPF</A>.<P>The processor clears the TF bit before invoking the handler. If TF=1 inthe flags image of a TSS at the time of a task switch, the exception occursafter the first instruction is executed in the new task.<P>The single-step flag is normally not cleared by privilege changes inside atask. <A HREF="INT.htm">INT</A> instructions, however, do clear TF. Therefore, softwaredebuggers that single-step code must recognize and emulate <A HREF="INT.htm">INT n</A> or <A HREF="INT.htm">INTO</A>rather than executing them directly.<P>To maintain protection, system software should check the current executionprivilege level after any single step interrupt to see whether singlestepping should continue at the current privilege level.<P>The interrupt priorities in hardware guarantee that if an externalinterrupt occurs, single stepping stops. When both an external interrupt anda single step interrupt occur together, the single step interrupt isprocessed first. This clears the TF bit. After saving the return address orswitching tasks, the external interrupt input is examined before the firstinstruction of the single step handler executes. If the external interruptis still pending, it is then serviced. The external interrupt handler is notsingle-stepped. To single step an interrupt handler, just single step an <A HREF="INT.htm">INT</A>n instruction that refers to the interrupt handler.<H3>12.3.1.5 Task Switch Breakpoint</H3>The debug exception also occurs after a switch to an 80386 task if theT-bit of the new TSS is set. The exception occurs after control has passedto the new task, but before the first instruction of that task is executed.The exception handler can detect this condition by examining the BT bit ofthe debug status register DR6.<P>Note that if the debug exception handler is a task, the T-bit of its TSSshould not be set. Failure to observe this rule will cause the processor toenter an infinite loop.<H2>12.3.2 Interrupt 3 -- Breakpoint Exception</H2>This exception is caused by execution of the breakpoint instruction <A HREF="INT.htm">INT</A> 3.Typically, a debugger prepares a breakpoint by substituting the opcode ofthe one-byte breakpoint instruction in place of the first opcode byte of theinstruction to be trapped. When execution of the <A HREF="INT.htm">INT</A> 3 instruction causesthe exception handler to be invoked, the saved value of ES:EIP points to thebyte following the <A HREF="INT.htm">INT</A> 3 instruction.<P>With prior generations of processors, this feature is used extensively fortrapping execution of specific instructions. With the 80386, the needsformerly filled by this feature are more conveniently solved via the debugregisters and interrupt 1. However, the breakpoint exception is stilluseful for debugging debuggers, because the breakpoint exception can vectorto a different exception handler than that used by the debugger. Thebreakpoint exception can also be useful when it is necessary to set agreater number of breakpoints than permitted by the debug registers.<P><HR><P><B>up:</B> <A HREF="c12.htm">Chapter 12 -- Debugging</A><BR><B>prev:</B> <A HREF="s12_02.htm">12.2 Debug Registers</A><BR><B>next:</B><A HREF="c13.htm">Chapter 13 -- Executing 80286 Protected-Mode Code</A> </BODY>⌨️ 快捷键说明
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