gp32.h

the test file for GP32 gameboy hack

/* RTC */
#define rRTCCON		(*(volatile unsigned char *)0x15700040)
#define rRTCALM		(*(volatile unsigned char *)0x15700050)
#define rALMSEC		(*(volatile unsigned char *)0x15700054)
#define rALMMIN		(*(volatile unsigned char *)0x15700058)
#define rALMHOUR	(*(volatile unsigned char *)0x1570005c)
#define rALMDAY		(*(volatile unsigned char *)0x15700060)
#define rALMMON		(*(volatile unsigned char *)0x15700064)
#define rALMYEAR	(*(volatile unsigned char *)0x15700068)
#define rRTCRST		(*(volatile unsigned char *)0x1570006c)
#define rBCDSEC		(*(volatile unsigned char *)0x15700070)
#define rBCDMIN		(*(volatile unsigned char *)0x15700074)
#define rBCDHOUR	(*(volatile unsigned char *)0x15700078)
#define rBCDDAY		(*(volatile unsigned char *)0x1570007c)
#define rBCDDATE	(*(volatile unsigned char *)0x15700080)
#define rBCDMON		(*(volatile unsigned char *)0x15700084)
#define rBCDYEAR	(*(volatile unsigned char *)0x15700088)
#define rTICINT		(*(volatile unsigned char *)0x15700044)

/* ADC */
#define rADCCON		(*(volatile unsigned *)0x15800000)
#define rADCDAT		(*(volatile unsigned *)0x15800004)

/* SPI */
#define rSPCON		(*(volatile unsigned *)0x15900000)
#define rSPSTA		(*(volatile unsigned *)0x15900004)
#define rSPPIN		(*(volatile unsigned *)0x15900008)
#define rSPPRE		(*(volatile unsigned *)0x1590000c)
#define rSPTDAT		(*(volatile unsigned *)0x15900010)
#define rSPRDAT		(*(volatile unsigned *)0x15900014)

/* MMC INTERFACE */
#define rMMCON		(*(volatile unsigned char *)0x15a00000)
#define rMMCRR		(*(volatile unsigned char *)0x15a00004)
#define rMMFCON		(*(volatile unsigned char *)0x15a00008)
#define rMMSTA		(*(volatile unsigned char *)0x15a0000c)
#define rMMFSTA		(*(volatile unsigned short *)0x15a00010)
#define rMMPRE		(*(volatile unsigned char *)0x15a00014)
#define rMMLEN		(*(volatile unsigned short *)0x15a00018)
#define rMMCR7		(*(volatile unsigned *)0x15a0001c)
#define rMMRSP0		(*(volatile unsigned *)0x15a00020)
#define rMMRSP1		(*(volatile unsigned *)0x15a00024)
#define rMMRSP2		(*(volatile unsigned *)0x15a00028)
#define rMMRSP3		(*(volatile unsigned *)0x15a0002c)
#define rMMCMD0		(*(volatile unsigned char *)0x15a00030)
#define rMMCMD1		(*(volatile unsigned *)0x15a00034)
#define rMMCR16		(*(volatile unsigned short *)0x15a00038)
#define rMMDAT		(*(volatile unsigned char *)0x15a0003c)

/* ISR */
#define pISR_RESET	(*(unsigned *)(_ISR_STARTADDRESS+0x0))
#define pISR_UNDEF	(*(unsigned *)(_ISR_STARTADDRESS+0x4))
#define pISR_SWI	(*(unsigned *)(_ISR_STARTADDRESS+0x8))
#define pISR_PABORT	(*(unsigned *)(_ISR_STARTADDRESS+0xc))
#define pISR_DABORT	(*(unsigned *)(_ISR_STARTADDRESS+0x10))
#define pISR_RESERVED	(*(unsigned *)(_ISR_STARTADDRESS+0x14))
#define pISR_IRQ	(*(unsigned *)(_ISR_STARTADDRESS+0x18))
#define pISR_FIQ	(*(unsigned *)(_ISR_STARTADDRESS+0x1c))

#define pISR_EINT0	(*(unsigned *)(_ISR_STARTADDRESS+0x20))
#define pISR_EINT1	(*(unsigned *)(_ISR_STARTADDRESS+0x24))
#define pISR_EINT2	(*(unsigned *)(_ISR_STARTADDRESS+0x28))
#define pISR_EINT3	(*(unsigned *)(_ISR_STARTADDRESS+0x2c))
#define pISR_EINT4	(*(unsigned *)(_ISR_STARTADDRESS+0x30))
#define pISR_EINT5	(*(unsigned *)(_ISR_STARTADDRESS+0x34))
#define pISR_EINT6	(*(unsigned *)(_ISR_STARTADDRESS+0x38))
#define pISR_EINT7	(*(unsigned *)(_ISR_STARTADDRESS+0x3c))
#define pISR_TICK	(*(unsigned *)(_ISR_STARTADDRESS+0x40))
#define pISR_WDT	(*(unsigned *)(_ISR_STARTADDRESS+0x44))
#define pISR_TIMER0	(*(unsigned *)(_ISR_STARTADDRESS+0x48))
#define pISR_TIMER1	(*(unsigned *)(_ISR_STARTADDRESS+0x4c))
#define pISR_TIMER2	(*(unsigned *)(_ISR_STARTADDRESS+0x50))
#define pISR_TIMER3	(*(unsigned *)(_ISR_STARTADDRESS+0x54))
#define pISR_TIMER4	(*(unsigned *)(_ISR_STARTADDRESS+0x58))
#define pISR_UERR01	(*(unsigned *)(_ISR_STARTADDRESS+0x5c))
#define pISR_NOTUSED	(*(unsigned *)(_ISR_STARTADDRESS+0x60))
#define pISR_DMA0	(*(unsigned *)(_ISR_STARTADDRESS+0x64))
#define pISR_DMA1	(*(unsigned *)(_ISR_STARTADDRESS+0x68))
#define pISR_DMA2	(*(unsigned *)(_ISR_STARTADDRESS+0x6c))
#define pISR_DMA3	(*(unsigned *)(_ISR_STARTADDRESS+0x70))
#define pISR_MMC	(*(unsigned *)(_ISR_STARTADDRESS+0x74))
#define pISR_SPI	(*(unsigned *)(_ISR_STARTADDRESS+0x78))
#define pISR_URXD0	(*(unsigned *)(_ISR_STARTADDRESS+0x7c))
#define pISR_URXD1	(*(unsigned *)(_ISR_STARTADDRESS+0x80))
#define pISR_USBD	(*(unsigned *)(_ISR_STARTADDRESS+0x84))
#define pISR_USBH	(*(unsigned *)(_ISR_STARTADDRESS+0x88))
#define pISR_IIC	(*(unsigned *)(_ISR_STARTADDRESS+0x8c))
#define pISR_UTXD0	(*(unsigned *)(_ISR_STARTADDRESS+0x90))
#define pISR_UTXD1	(*(unsigned *)(_ISR_STARTADDRESS+0x94))
#define pISR_RTC	(*(unsigned *)(_ISR_STARTADDRESS+0x98))
#define pISR_ADC	(*(unsigned *)(_ISR_STARTADDRESS+0xa0))

/* PENDING BIT */
#define BIT_EINT0	(0x1)
#define BIT_EINT1	(0x1<<1)
#define BIT_EINT2	(0x1<<2)
#define BIT_EINT3	(0x1<<3)
#define BIT_EINT4	(0x1<<4)
#define BIT_EINT5	(0x1<<5)
#define BIT_EINT6	(0x1<<6)
#define BIT_EINT7	(0x1<<7)
#define BIT_TICK	(0x1<<8)
#define BIT_WDT		(0x1<<9)
#define BIT_TIMER0	(0x1<<10)
#define BIT_TIMER1	(0x1<<11)
#define BIT_TIMER2	(0x1<<12)
#define BIT_TIMER3	(0x1<<13)
#define BIT_TIMER4	(0x1<<14)
#define BIT_UERR01	(0x1<<15)
#define BIT_NOTUSED	(0x1<<16)
#define BIT_DMA0	(0x1<<17)
#define BIT_DMA1	(0x1<<18)
#define BIT_DMA2	(0x1<<19)
#define BIT_DMA3	(0x1<<20)
#define BIT_MMC		(0x1<<21)
#define BIT_SPI		(0x1<<22)
#define BIT_URXD0	(0x1<<23)
#define BIT_URXD1	(0x1<<24)
#define BIT_USBD	(0x1<<25)
#define BIT_USBH	(0x1<<26)
#define BIT_IIC		(0x1<<27)
#define BIT_UTXD0	(0x1<<28)
#define BIT_UTXD1	(0x1<<29)
#define BIT_RTC		(0x1<<30)
#define BIT_ADC		(0x1<<31)
#define BIT_ALLMSK	(0xffffffff)

#define ClearPending(bit) {\
		 rSRCPND = bit;\
		 rINTPND = bit;\
		 rINTPND;\
		 }
//Wait until rINTPND is changed for the case that the ISR is very short.


//////////////////////////////////////////////////////////////////////////////
// Typedefs                                                                 //
//////////////////////////////////////////////////////////////////////////////
typedef struct
{
	unsigned STOP_BIT:1;	// Enters STOP mode. This bit isn't be cleared automatically.
	unsigned SL_IDLE:1;		// SL_IDLE mode option. This bit isn't be cleared automatically. To enter SL_IDLE mode, CLKCON register has to be 0xe.
	unsigned IDLE_BIT:1;	// Enters IDLE mode. This bit isn't be cleared automatically.
	unsigned LCDC:1;		// Controls HCLK into LCDC block
	unsigned USB_host:1;	// Controls HCLK into USB host block
	unsigned USB_device:1;	// Controls PCLK into USB device block
	unsigned PWMTIMER:1;	// Controls PCLK into PWMTIMER block
	unsigned MMC:1;			// Controls PCLK into MMC interface block
	unsigned UART0:1;		// Controls PCLK into UART0 block
	unsigned UART1:1;		// Controls PCLK into UART1 block
	unsigned GPIO:1;		// Controls PCLK into GPIO block
	unsigned RTC:1;			// Controls PCLK into RTC control block. Even if this bit is cleared to 0, RTC timer is alive.
	unsigned ADC:1;			// Controls PCLK into ADC block
	unsigned IIC:1;			// Controls PCLK into IIC block
	unsigned IIS:1;			// Controls PCLK into IIS block
	unsigned SPI:1;			// Controls PCLK into SPI block
} CLKCON;

typedef struct
{
	unsigned ENVID:1;		// LCD video output and the logic 1=enable/0=disable.
	unsigned BPPMODE:4;		// 1011 = 8 bpp for TFT, 1100 = 16 bpp for TFT
	unsigned PNRMODE:2;		// TFT: 3
	unsigned MMODE:1;		// This bit determines the toggle rate of the VM. 0 = Each Frame, 1 = The rate defined by the MVAL
	unsigned CLKVAL:10;		// TFT: VCLK = HCLK / [(CLKVAL+1) x 2] (CLKVAL >= 1)
	unsigned LINECNT:10;	// (read only) These bits provide the status of the line counter. Down count from LINEVAL to 0
} LCDCON1;

typedef struct
{
	unsigned VSPW:6;		// TFT: Vertical sync pulse width determines the VSYNC pulse's high level width by counting the number of inactive lines.
	unsigned VFPD:8;		// TFT: Vertical front porch is the number of inactive lines at the end of a frame, before vertical synchronization period.
	unsigned LINEVAL:10;	// TFT/STN: These bits determine the vertical size of LCD panel.
	unsigned VBPD:8;		// TFT: Vertical back porch is the number of inactive lines at the start of a frame, after vertical synchronization period.
} LCDCON2;

typedef struct
{
	unsigned HFPD:8;		// TFT: Horizontal front porch is the number of VCLK periods between the end of active data and the rising edge of HSYNC.
	unsigned HOZVAL:11;		// TFT/STN: These bits determine the horizontal size of LCD panel. 2n bytes.
	unsigned HBPD:7;		// TFT: Horizontal back porch is the number of VCLK periods between the falling edge of HSYNC and the start of active data.
} LCDCON3;

typedef struct
{
	unsigned HSPW:8;		// TFT: Horizontal sync pulse width determines the HSYNC pulse's high level width by counting the number of the VCLK.
	unsigned MVAL:8;		// STN:
	unsigned ADDVAL:8;		// TFT: Palette Index offset value
	unsigned PALADDEN:1;	// TFT: Palette Index offset enable. 0 = Disable 1 = Enable
} LCDCON4;

typedef struct
{
	unsigned HWSWP:1;		// STN/TFT: Half-Word swap control bit. 0 = Swap Disable 1 = Swap Enable
	unsigned BSWP:1;		// STN/TFT: Byte swap control bit. 0 = Swap Disable 1 = Swap Enable
	unsigned ENLEND:1;		// TFT: LEND output signal enable/disable. 0 = Disable LEND signal. 1 = Enable LEND signal
	unsigned RESERVED1:1;
	unsigned INVENDLINE:1;	// TFT: This bit indicates the LEND signal polarity. 0 = normal 1 = inverted
	unsigned RESERVED2:1;
	unsigned INVVDEN:1;		// TFT: This bit indicates the VDEN signal polarity. 0 = normal 1 = inverted
	unsigned INVVD:1;		// STN/TFT: This bit indicates the VD (video data) pulse polarity. 0 = Normal. 1 = VD is inverted.
	unsigned INVVFRAME:1;	// STN/TFT: This bit indicates the VFRAME/VSYNC pulse polarity. 0 = normal 1 = inverted
	unsigned INVVLINE:1;	// STN/TFT: This bit indicates the VLINE/HSYNC pulse polarity. 0 = normal 1 = inverted
	unsigned INVVCLK:1;		// STN/TFT: This bit controls the polarity of the VCLK active edge. 0 = The video data is fetched at VCLK falling edge. 1 = The video data is fetched at VCLK rising edge
	unsigned RESERVED3:2;
	unsigned SELFREF:1;		// STN:
	unsigned SLOWCLKSYNC:1;	// STN:
	unsigned RESERVED4:2;	// must be 0
	unsigned HSTATUS:2;		// TFT: Horizontal Status (Read only) 00 = HSYNC 01 = BACK Porch. 10 = ACTIVE 11 = FRONT Porch
	unsigned VSTATUS:2;		// TFT: Vertical Status (Read only). 00 = VSYNC 01 = BACK Porch. 10 = ACTIVE 11 = FRONT Porch
} LCDCON5;

typedef struct
{
	unsigned LCDBASEU:21;	// For single-scan LCD: These bits indicate A[21:1] of the start address of the LCD frame buffer.
	unsigned LCDBANK:7;		// A[28:22]
} LCDSADDR1;

typedef struct
{
	unsigned LCDBASEL:21;	// For single scan LCD: These bits indicate A[21:1] of the end address of the LCD frame buffer. LCDBASEL = ((the fame end address) >>1) + 1 = LCDBASEU + (PAGEWIDTH+OFFSIZE)x(LINEVAL+1)
} LCDSADDR2;

typedef struct
{
	unsigned PAGEWIDTH:11;	// Virtual screen page width(the number of half words) This value defines the width of the view port in the frame
	unsigned OFFSIZE:11;	// Virtual screen offset size(the number of half words) This value defines the difference between the address of the last half word displayed on the previous LCD line and the address of the first half word to be displayed in the new LCD line.
} LCDSADDR3;




#endif	// __GP32_H