setup.tcl

来自「這是一堆verilog的source code.包含許多常用的小電路.還不錯用.」· TCL 代码 · 共 14 行

# SETUP
  # SET CLOCK PERIOD
  set register2register 1000
  set input2register 1000
  set register2output 1000
  set input2output 1000

  # SETUP TECHNOLOGY
  set part S30PQ208
  set process 3
  set wire_table s10-3_wc
  load_library xis