spectrum.tcl

来自「這是一堆verilog的source code.包含許多常用的小電路.還不錯用.」· TCL 代码 · 共 29 行

# Helper function
proc renoir_eval {x} {
   if {[string length [info commands exemplar_eval]] != 0} {
      exemplar_eval ""
   } else {
      eval ""
   }
}


puts "Info: Renoir Synthesis run started"

# SETUP
source "E:/TOOLS/Verilog_code/timing/ls/intra_assignment_intra_assignment/scripts/setup.tcl"
renoir_eval ""

# READ IN SOURCE FILES
source "E:/TOOLS/Verilog_code/timing/ls/intra_assignment_intra_assignment/scripts/open_files.tcl"
renoir_eval ""

# OPTIMIZE
source "E:/TOOLS/Verilog_code/timing/ls/intra_assignment_intra_assignment/scripts/optimize.tcl"

# PLACE AND ROUTE COMMAND
set_working_dir "E:/TOOLS/Verilog_code/timing/ls/intra_assignment_intra_assignment/netlists"
place_and_route "E:/TOOLS/Verilog_code/timing/ls/intra_assignment_intra_assignment/netlists/intra_assignment.edf" -exe_path "" -target "xis" -part S30PQ208 -speed_grade 3 -ba_format Verilog


puts "Info: Renoir Synthesis run finished"