optimize.tcl

這是一堆verilog的source code.包含許多常用的小電路.還不錯用.

# OPTIMIZE
  set effort standard
  set area false
  set delay true
  set chip true
  set macro false
  set hierarchy_auto true
  set hierarchy_preserve false

  optimize .timing.intra_assignment.INTERFACE -target xis -effort standard -delay -chip -hierarchy auto
  optimize_timing .timing.intra_assignment.INTERFACE

  # WRITE DESIGN NETLIST
  auto_write -format edif "E:/TOOLS/Verilog_code/timing/ls/intra_assignment_intra_assignment/netlists/intra_assignment.edf"

  # WRITE XDB FILE
  auto_write -format xdb "E:/TOOLS/Verilog_code/timing/ls/intra_assignment_intra_assignment/xdb/intra_assignment.xdb"

  # WRITE REPORTS
  report_area -cell_usage > "E:/TOOLS/Verilog_code/timing/ls/intra_assignment_intra_assignment/reports/intra_assignment_sum.txt"
  report_delay -num_paths 1 -clock_frequency >> "E:/TOOLS/Verilog_code/timing/ls/intra_assignment_intra_assignment/reports/intra_assignment_sum.txt"

  set output_file "E:/TOOLS/Verilog_code/timing/ls/intra_assignment_intra_assignment/netlists/intra_assignment.edf"