intra_assignment.v

這是一堆verilog的source code.包含許多常用的小電路.還不錯用.

// renoir header_start
//
// Module timing.intra_assignment.intra_assignment
//
// Created:
//          by - Administrator.UNKNOWN (LMC)
//          at - 08:36:19 AM 01/12/2002
//
// Generated by Mentor Graphics' Renoir(TM) 2000.3 (Build 2)
//
// renoir header_end

`resetall
`timescale 1ns/10ps
module intra_assignment(q1,q2,d,clk);


// Internal Declarations

	input 	clk;
	output 	q1,q2;

	inout 	d;
	
	reg		q1,q2,d;

// renoir interface_end

	always @ (posedge clk)
	begin 
		q1 = #2 d;
		q2 = #3 d;
	end

	always @ (posedge clk)
	begin 
		d <= ~d;
	end


endmodule